[PATCH] D81524: AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: foad, nhaehnle, kerbowa, rampitec.
Herald added subscribers: hiraditya, t-tye, tpr, dstuttard, rovka, yaxunl, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.
arsenm added a parent revision: D81523: AMDGPU/GlobalISel: Workaround some load/store type selection patterns.

These are legal since we can do a 96-bit load on some subtargets, but
this is only for vector loads. If we can't widen the load, it needs to
be broken down once known scalar. For 16-byte alignment, widen to a
128-bit load.


https://reviews.llvm.org/D81524

Files:
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir

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