[PATCH] D81488: [MSP430] Enable some basic support for debug information

[Anatoly Trosinenko via Phabricator via llvm-commits]

atrosinenko created this revision.
atrosinenko added reviewers: echristo, spatel.
Herald added subscribers: hiraditya, aprantl.
Herald added a project: LLVM.

This commit technically permits LLVM to emit the debug information for ELF files for MSP430 architecture. Aside from this, it only defines the register numbers as defined by part 10.1 of MSP430 EABI specification (assuming the 1-byte subregisters share the register numbers with corresponding full-size registers).

This commit was basically tested by me with TI-provided GCC 8.3.1 toolchain by compiling an example program with `clang` (please note manual linking may be required due to upstream `clang` not yet handling the `-msim` option necessary to run binaries on the GDB-provided simulator) and then running it and single-stepping with `msp430-elf-gdb` like this:

  $sysroot/bin/msp430-elf-gdb ./test -ex "target sim" -ex "load ./test"
  (gdb) ... traditional GDB commands follow ...

While this implementation is most probably far from completeness and is considered experimental, it can already help with debugging MSP430 programs as well as finding issues in LLVM debug info support for MSP430 itself.

One of the use cases includes trying to find a point where UBSan check in a trap-on-error mode was triggered.

The expected debug information format is described in the MSP430 Embedded Application Binary Interface <http://www.ti.com/lit/an/slaa534/slaa534.pdf> specification, part 10.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81488

Files:
  llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
  llvm/lib/Target/MSP430/MSP430RegisterInfo.td


Index: llvm/lib/Target/MSP430/MSP430RegisterInfo.td
===================================================================
--- llvm/lib/Target/MSP430/MSP430RegisterInfo.td
+++ llvm/lib/Target/MSP430/MSP430RegisterInfo.td
@@ -15,6 +15,7 @@
   let Namespace = "MSP430";
   let HWEncoding{3-0} = num;
   let AltNames = alt;
+  let DwarfNumbers = [num];
 }
 
 class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs,
@@ -24,6 +25,7 @@
   let Namespace = "MSP430";
   let HWEncoding{3-0} = num;
   let AltNames = alt;
+  let DwarfNumbers = [num];
 }
 
 //===----------------------------------------------------------------------===//
Index: llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
===================================================================
--- llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
+++ llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
@@ -24,4 +24,6 @@
 
   AlignmentIsInBytes = false;
   UsesELFSectionDirectiveForBSS = true;
+
+  SupportsDebugInformation = true;
 }


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