[llvm] b641c9f - [VE] Support rest of load/store instructions in MC layer
Simon Moll via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 9 05:21:27 PDT 2020
Author: Kazushi (Jam) Marukawa
Date: 2020-06-09T14:21:00+02:00
New Revision: b641c9f729fe4ebbc3e737fa69d3d9caf1cb3632
URL: https://github.com/llvm/llvm-project/commit/b641c9f729fe4ebbc3e737fa69d3d9caf1cb3632
DIFF: https://github.com/llvm/llvm-project/commit/b641c9f729fe4ebbc3e737fa69d3d9caf1cb3632.diff
LOG: [VE] Support rest of load/store instructions in MC layer
Summary:
Add DLD/DLDU/DLDL/PFCH/TS1AM/TS2AM/TS3AM/ATMAM/CAS instructions newly.
Add regression tests for them to asmparser, mccodeemitter, and disassembler.
In order to add those instructions, change asmparser to support UImm0to2 and
UImm1 operands, add new decode functions to disassembler, and add new print
functions to instprinter.
Differential Revision: https://reviews.llvm.org/D81454
Added:
llvm/test/MC/VE/ATMAM.s
llvm/test/MC/VE/CAS.s
llvm/test/MC/VE/DLD.s
llvm/test/MC/VE/PFCH.s
llvm/test/MC/VE/TS1AM.s
llvm/test/MC/VE/TS2AM.s
llvm/test/MC/VE/TS3AM.s
Modified:
llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp
llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h
llvm/lib/Target/VE/VEInstrFormats.td
llvm/lib/Target/VE/VEInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
index fb54be9b3a1f..9af3d9b9cda6 100644
--- a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
+++ b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
@@ -218,6 +218,28 @@ class VEOperand : public MCParsedAsmOperand {
}
return false;
}
+ bool isUImm0to2() {
+ if (!isImm())
+ return false;
+
+ // Constant case
+ if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
+ int64_t Value = ConstExpr->getValue();
+ return Value >= 0 && Value < 3;
+ }
+ return false;
+ }
+ bool isUImm1() {
+ if (!isImm())
+ return false;
+
+ // Constant case
+ if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
+ int64_t Value = ConstExpr->getValue();
+ return isUInt<1>(Value);
+ }
+ return false;
+ }
bool isUImm2() {
if (!isImm())
return false;
@@ -415,6 +437,14 @@ class VEOperand : public MCParsedAsmOperand {
addImmOperands(Inst, N);
}
+ void addUImm0to2Operands(MCInst &Inst, unsigned N) const {
+ addImmOperands(Inst, N);
+ }
+
+ void addUImm1Operands(MCInst &Inst, unsigned N) const {
+ addImmOperands(Inst, N);
+ }
+
void addUImm2Operands(MCInst &Inst, unsigned N) const {
addImmOperands(Inst, N);
}
diff --git a/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp b/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
index 88fe7fab5620..5196d9aa56e7 100644
--- a/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
+++ b/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp
@@ -157,6 +157,8 @@ static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeASX(MCInst &Inst, uint64_t insn, uint64_t Address,
+ const void *Decoder);
static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,
@@ -169,6 +171,14 @@ static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeTS1AMI64(MCInst &Inst, uint64_t insn,
+ uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeTS1AMI32(MCInst &Inst, uint64_t insn,
+ uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeCASI64(MCInst &Inst, uint64_t insn, uint64_t Address,
+ const void *Decoder);
+static DecodeStatus DecodeCASI32(MCInst &Inst, uint64_t insn, uint64_t Address,
+ const void *Decoder);
static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeSIMM7(MCInst &Inst, uint64_t insn, uint64_t Address,
@@ -342,6 +352,68 @@ static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass);
}
+static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address,
+ const void *Decoder, bool isImmOnly, bool isUImm,
+ DecodeFunc DecodeSX) {
+ unsigned sx = fieldFromInstruction(insn, 48, 7);
+ bool cy = fieldFromInstruction(insn, 47, 1);
+ unsigned sy = fieldFromInstruction(insn, 40, 7);
+
+ // Add $sx.
+ DecodeStatus status;
+ status = DecodeSX(MI, sx, Address, Decoder);
+ if (status != MCDisassembler::Success)
+ return status;
+
+ // Add $disp($sz).
+ status = DecodeAS(MI, insn, Address, Decoder);
+ if (status != MCDisassembler::Success)
+ return status;
+
+ // Add $sy.
+ if (cy && !isImmOnly) {
+ status = DecodeSX(MI, sy, Address, Decoder);
+ if (status != MCDisassembler::Success)
+ return status;
+ } else {
+ if (isUImm)
+ MI.addOperand(MCOperand::createImm(sy));
+ else
+ MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));
+ }
+
+ // Add $sd.
+ status = DecodeSX(MI, sx, Address, Decoder);
+ if (status != MCDisassembler::Success)
+ return status;
+
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeTS1AMI64(MCInst &MI, uint64_t insn, uint64_t Address,
+ const void *Decoder) {
+ return DecodeCAS(MI, insn, Address, Decoder, false, true,
+ DecodeI64RegisterClass);
+}
+
+static DecodeStatus DecodeTS1AMI32(MCInst &MI, uint64_t insn, uint64_t Address,
+ const void *Decoder) {
+ return DecodeCAS(MI, insn, Address, Decoder, false, true,
+ DecodeI32RegisterClass);
+}
+
+static DecodeStatus DecodeCASI64(MCInst &MI, uint64_t insn, uint64_t Address,
+ const void *Decoder) {
+ return DecodeCAS(MI, insn, Address, Decoder, false, false,
+ DecodeI64RegisterClass);
+}
+
+static DecodeStatus DecodeCASI32(MCInst &MI, uint64_t insn, uint64_t Address,
+ const void *Decoder) {
+ return DecodeCAS(MI, insn, Address, Decoder, false, false,
+ DecodeI32RegisterClass);
+}
+
static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address,
const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass);
diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp
index 324f3bbe8a91..38be2b4fa2f8 100644
--- a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp
+++ b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp
@@ -150,6 +150,37 @@ void VEInstPrinter::printMemASOperandASX(const MCInst *MI, int OpNum,
}
}
+void VEInstPrinter::printMemASOperandRRM(const MCInst *MI, int OpNum,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O, const char *Modifier) {
+ // If this is an ADD operand, emit it like normal operands.
+ if (Modifier && !strcmp(Modifier, "arith")) {
+ printOperand(MI, OpNum, STI, O);
+ O << ", ";
+ printOperand(MI, OpNum + 1, STI, O);
+ return;
+ }
+
+ if (MI->getOperand(OpNum + 1).isImm() &&
+ MI->getOperand(OpNum + 1).getImm() == 0) {
+ // don't print "+0"
+ } else {
+ printOperand(MI, OpNum + 1, STI, O);
+ }
+ if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) {
+ if (MI->getOperand(OpNum + 1).isImm() &&
+ MI->getOperand(OpNum + 1).getImm() == 0) {
+ O << "0";
+ } else {
+ // don't print "(0)"
+ }
+ } else {
+ O << "(";
+ printOperand(MI, OpNum, STI, O);
+ O << ")";
+ }
+}
+
void VEInstPrinter::printMemASOperand(const MCInst *MI, int OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O, const char *Modifier) {
diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h
index 39e7d0b9a991..6c1819ec8b14 100644
--- a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h
+++ b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h
@@ -44,6 +44,9 @@ class VEInstPrinter : public MCInstPrinter {
void printMemASOperandASX(const MCInst *MI, int OpNum,
const MCSubtargetInfo &STI, raw_ostream &OS,
const char *Modifier = nullptr);
+ void printMemASOperandRRM(const MCInst *MI, int OpNum,
+ const MCSubtargetInfo &STI, raw_ostream &OS,
+ const char *Modifier = nullptr);
void printMemASOperand(const MCInst *MI, int OpNum,
const MCSubtargetInfo &STI, raw_ostream &OS,
const char *Modifier = nullptr);
diff --git a/llvm/lib/Target/VE/VEInstrFormats.td b/llvm/lib/Target/VE/VEInstrFormats.td
index d5a63e70dc9a..60cf1d58b37b 100644
--- a/llvm/lib/Target/VE/VEInstrFormats.td
+++ b/llvm/lib/Target/VE/VEInstrFormats.td
@@ -67,8 +67,15 @@ class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
//-----------------------------------------------------------------------------
// Section 5.2 RRM Type
+//
+// RRM type is identical to RM, but the effective address is generated
+// by sz + imm32. The sy field is used by other purposes.
//-----------------------------------------------------------------------------
+class RRM<bits<8>opVal, dag outs, dag ins, string asmstr,
+ list<dag> pattern = []>
+ : RM<opVal, outs, ins, asmstr, pattern>;
+
//-----------------------------------------------------------------------------
// Section 5.3 CF Type
//
diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td
index 60dde1d68456..5f60e87b1df7 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.td
+++ b/llvm/lib/Target/VE/VEInstrInfo.td
@@ -121,9 +121,23 @@ def zero : Operand<i32>, PatLeaf<(imm), [{
let ParserMatchClass = ZeroAsmOperand;
}
+// uimm0to2 - Special immediate value represents 0, 1, and 2.
+def UImm0to2AsmOperand : AsmOperandClass {
+ let Name = "UImm0to2";
+}
+def uimm0to2 : Operand<i32>, PatLeaf<(imm), [{
+ return N->getZExtValue() < 3; }], ULO7> {
+ let ParserMatchClass = UImm0to2AsmOperand;
+}
+
// uimm1 - Generic immediate value.
+def UImm1AsmOperand : AsmOperandClass {
+ let Name = "UImm1";
+}
def uimm1 : Operand<i32>, PatLeaf<(imm), [{
- return isUInt<1>(N->getZExtValue()); }]>;
+ return isUInt<1>(N->getZExtValue()); }], ULO7> {
+ let ParserMatchClass = UImm1AsmOperand;
+}
// uimm2 - Generic immediate value.
def UImm2AsmOperand : AsmOperandClass {
@@ -261,16 +275,18 @@ def CCUIOp : PatLeaf<(cond), [{
// MEMrri, MEMrii, MEMzri, MEMzii
// AS format:
// MEMriASX, MEMziASX : simple AS format
+// MEMriRRM, MEMziRRM : AS format in RRM format
// well be added later.
+// DAG selections for both ASX and AS formats.
def ADDRrri : ComplexPattern<iPTR, 3, "selectADDRrri", [frameindex], []>;
def ADDRrii : ComplexPattern<iPTR, 3, "selectADDRrii", [frameindex], []>;
def ADDRzri : ComplexPattern<iPTR, 3, "selectADDRzri", [], []>;
def ADDRzii : ComplexPattern<iPTR, 3, "selectADDRzii", [], []>;
-// AS format:
def ADDRri : ComplexPattern<iPTR, 2, "selectADDRri", [frameindex], []>;
-//
-// ASX assembly instruction format:
+def ADDRzi : ComplexPattern<iPTR, 2, "selectADDRzi", [], []>;
+
+// ASX format.
def VEMEMrriAsmOperand : AsmOperandClass {
let Name = "MEMrri";
let ParserMethod = "parseMEMOperand";
@@ -287,6 +303,8 @@ def VEMEMziiAsmOperand : AsmOperandClass {
let Name = "MEMzii";
let ParserMethod = "parseMEMOperand";
}
+
+// ASX format uses single assembly instruction format.
def MEMrri : Operand<iPTR> {
let PrintMethod = "printMemASXOperand";
let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
@@ -307,7 +325,8 @@ def MEMzii : Operand<iPTR> {
let MIOperandInfo = (ops i32imm /* = 0 */, i32imm, i32imm);
let ParserMatchClass = VEMEMziiAsmOperand;
}
-// AS assembly instruction format:
+
+// AS format.
def VEMEMriAsmOperand : AsmOperandClass {
let Name = "MEMri";
let ParserMethod = "parseMEMAsOperand";
@@ -316,7 +335,9 @@ def VEMEMziAsmOperand : AsmOperandClass {
let Name = "MEMzi";
let ParserMethod = "parseMEMAsOperand";
}
-// AS generic assembly instruction format:
+
+// AS format uses multiple assembly instruction formats
+// 1. AS generic assembly instruction format:
def MEMriASX : Operand<iPTR> {
let PrintMethod = "printMemASOperandASX";
let MIOperandInfo = (ops ptr_rc, i32imm);
@@ -327,6 +348,19 @@ def MEMziASX : Operand<iPTR> {
let MIOperandInfo = (ops i32imm /* = 0 */, i32imm);
let ParserMatchClass = VEMEMziAsmOperand;
}
+
+// 2. AS RRM style assembly instruction format:
+def MEMriRRM : Operand<iPTR> {
+ let PrintMethod = "printMemASOperandRRM";
+ let MIOperandInfo = (ops ptr_rc, i32imm);
+ let ParserMatchClass = VEMEMriAsmOperand;
+}
+def MEMziRRM : Operand<iPTR> {
+ let PrintMethod = "printMemASOperandRRM";
+ let MIOperandInfo = (ops i32imm /* = 0 */, i32imm);
+ let ParserMatchClass = VEMEMziAsmOperand;
+}
+
def MEMASri : Operand<iPTR> {
let PrintMethod = "printMemASOperand";
let MIOperandInfo = (ops ptr_rc, i32imm);
@@ -677,6 +711,45 @@ multiclass CVTm<string opcStr, bits<8> opc, RegisterClass RCo, ValueType Tyo,
!strconcat(opcStr, " $sx, $sy")>;
}
+// Multiclass for PFCH instructions.
+// e.g. PFCH
+let sx = 0, hasSideEffects = 0 in
+multiclass PFCHm<string opcStr, bits<8>opc> {
+ def rri : RM<opc, (outs), (ins MEMrri:$addr), !strconcat(opcStr, " $addr"),
+ [(prefetch ADDRrri:$addr, imm, imm, (i32 1))]>;
+ let cy = 0 in
+ def rii : RM<opc, (outs), (ins MEMrii:$addr), !strconcat(opcStr, " $addr"),
+ [(prefetch ADDRrii:$addr, imm, imm, (i32 1))]>;
+ let cz = 0 in
+ def zri : RM<opc, (outs), (ins MEMzri:$addr), !strconcat(opcStr, " $addr"),
+ [(prefetch ADDRzri:$addr, imm, imm, (i32 1))]>;
+ let cy = 0, cz = 0 in
+ def zii : RM<opc, (outs), (ins MEMzii:$addr), !strconcat(opcStr, " $addr"),
+ [(prefetch ADDRzii:$addr, imm, imm, (i32 1))]>;
+}
+
+// Multiclass for CAS instructions.
+// e.g. TS1AML, TS1AMW, TS2AM, and etc.
+let Constraints = "$dest = $sd", DisableEncoding = "$sd",
+ mayStore=1, mayLoad = 1, hasSideEffects = 0 in
+multiclass RRCAStgm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty,
+ Operand immOp, Operand MEM, Operand ADDR,
+ SDPatternOperator OpNode = null_frag> {
+ def r : RRM<opc, (outs RC:$dest), (ins MEM:$addr, RC:$sy, RC:$sd),
+ !strconcat(opcStr, " $dest, $addr, $sy"),
+ [(set Ty:$dest, (OpNode ADDR:$addr, Ty:$sy, Ty:$sd))]>;
+ let cy = 0 in
+ def i : RRM<opc, (outs RC:$dest), (ins MEM:$addr, immOp:$sy, RC:$sd),
+ !strconcat(opcStr, " $dest, $addr, $sy"),
+ [(set Ty:$dest, (OpNode ADDR:$addr, (Ty immOp:$sy), Ty:$sd))]>;
+}
+multiclass RRCASm<string opcStr, bits<8>opc, RegisterClass RC, ValueType Ty,
+ Operand immOp, SDPatternOperator OpNode = null_frag> {
+ defm ri : RRCAStgm<opcStr, opc, RC, Ty, immOp, MEMriRRM, ADDRri, OpNode>;
+ let cz = 0 in
+ defm zi : RRCAStgm<opcStr, opc, RC, Ty, immOp, MEMziRRM, ADDRzi, OpNode>;
+}
+
// Multiclass for branch instructions
// e.g. BCFL, BCFW, BCFD, and etc.
let isBranch = 1, isTerminator = 1, isIndirectBranch = 1, hasSideEffects = 0 in
@@ -927,14 +1000,46 @@ let DecoderMethod = "DecodeStoreI32" in
defm ST1B : STOREm<"st1b", 0x15, I32, i32, truncstorei8>;
// Section 8.2.12 - DLDS
+let DecoderMethod = "DecodeLoadI64" in
+defm DLD : LOADm<"dld", 0x09, I64, i64, load>;
+
// Section 8.2.13 - DLDU
+let DecoderMethod = "DecodeLoadF32" in
+defm DLDU : LOADm<"dldu", 0x0a, F32, f32, load>;
+
// Section 8.2.14 - DLDL
+let DecoderMethod = "DecodeLoadI32" in
+defm DLDLSX : LOADm<"dldl.sx", 0x0b, I32, i32, load>;
+let cx = 1, DecoderMethod = "DecodeLoadI32" in
+defm DLDLZX : LOADm<"dldl.zx", 0x0b, I32, i32, load>;
+
// Section 8.2.15 - PFCH
+let DecoderMethod = "DecodeASX" in
+defm PFCH : PFCHm<"pfch", 0x0c>;
+
// Section 8.2.16 - TS1AM (Test and Set 1 AM)
+let DecoderMethod = "DecodeTS1AMI64" in
+defm TS1AML : RRCASm<"ts1am.l", 0x42, I64, i64, uimm7>;
+let DecoderMethod = "DecodeTS1AMI32", cx = 1 in
+defm TS1AMW : RRCASm<"ts1am.w", 0x42, I32, i32, uimm7>;
+
// Section 8.2.17 - TS2AM (Test and Set 2 AM)
+let DecoderMethod = "DecodeTS1AMI64" in
+defm TS2AM : RRCASm<"ts2am", 0x43, I64, i64, uimm7>;
+
// Section 8.2.18 - TS3AM (Test and Set 3 AM)
+let DecoderMethod = "DecodeTS1AMI64" in
+defm TS3AM : RRCASm<"ts3am", 0x52, I64, i64, uimm1>;
+
// Section 8.2.19 - ATMAM (Atomic AM)
+let DecoderMethod = "DecodeTS1AMI64" in
+defm ATMAM : RRCASm<"atmam", 0x53, I64, i64, uimm0to2>;
+
// Section 8.2.20 - CAS (Compare and Swap)
+let DecoderMethod = "DecodeCASI64" in
+defm CASL : RRCASm<"cas.l", 0x62, I64, i64, simm7>;
+let DecoderMethod = "DecodeCASI32", cx = 1 in
+defm CASW : RRCASm<"cas.w", 0x62, I32, i32, simm7>;
//-----------------------------------------------------------------------------
// Section 8.3 - Transfer Control Instructions
diff --git a/llvm/test/MC/VE/ATMAM.s b/llvm/test/MC/VE/ATMAM.s
new file mode 100644
index 000000000000..67f623cabc8c
--- /dev/null
+++ b/llvm/test/MC/VE/ATMAM.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: atmam %s20, 20(%s11), %s32
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0xa0,0x14,0x53]
+atmam %s20, 20(%s11), %s32
+
+# CHECK-INST: atmam %s20, 8192, 0
+# CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x00,0x00,0x14,0x53]
+atmam %s20, 8192, 0
+
+# CHECK-INST: atmam %s20, 8192, 1
+# CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x00,0x01,0x14,0x53]
+atmam %s20, 8192, 1
+
+# CHECK-INST: atmam %s20, 8192, 2
+# CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x00,0x02,0x14,0x53]
+atmam %s20, 8192, 2
diff --git a/llvm/test/MC/VE/CAS.s b/llvm/test/MC/VE/CAS.s
new file mode 100644
index 000000000000..d978d98db621
--- /dev/null
+++ b/llvm/test/MC/VE/CAS.s
@@ -0,0 +1,16 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: cas.l %s20, 20(%s11), %s32
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0xa0,0x14,0x62]
+cas.l %s20, 20(%s11), %s32
+
+# CHECK-INST: cas.w %s20, 8192, 63
+# CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x00,0x3f,0x94,0x62]
+cas.w %s20, 8192, 63
+
+# CHECK-INST: cas.w %s20, 8192, -64
+# CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x00,0x40,0x94,0x62]
+cas.w %s20, 8192, -64
diff --git a/llvm/test/MC/VE/DLD.s b/llvm/test/MC/VE/DLD.s
new file mode 100644
index 000000000000..4896545979d2
--- /dev/null
+++ b/llvm/test/MC/VE/DLD.s
@@ -0,0 +1,32 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: dld %s11, 8199
+# CHECK-ENCODING: encoding: [0x07,0x20,0x00,0x00,0x00,0x00,0x0b,0x09]
+dld %s11, 8199
+
+# CHECK-INST: dld %s11, 20(%s11)
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x00,0x8b,0x0b,0x09]
+dld %s11, 20(%s11)
+
+# CHECK-INST: dld %s11, -1(, %s11)
+# CHECK-ENCODING: encoding: [0xff,0xff,0xff,0xff,0x8b,0x00,0x0b,0x09]
+dld %s11, -1(, %s11)
+
+# CHECK-INST: dld %s11, 20(%s10, %s11)
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x09]
+dld %s11, 20(%s10, %s11)
+
+# CHECK-INST: dldu %s11, 20(%s10, %s11)
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x0a]
+dldu %s11, 20(%s10, %s11)
+
+# CHECK-INST: dldl.sx %s11, 20(%s10, %s11)
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x0b]
+dldl.sx %s11, 20(%s10, %s11)
+
+# CHECK-INST: dldl.zx %s11, 20(%s10, %s11)
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x8b,0x0b]
+dldl.zx %s11, 20(%s10, %s11)
diff --git a/llvm/test/MC/VE/PFCH.s b/llvm/test/MC/VE/PFCH.s
new file mode 100644
index 000000000000..0005939775b7
--- /dev/null
+++ b/llvm/test/MC/VE/PFCH.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: pfch 8199
+# CHECK-ENCODING: encoding: [0x07,0x20,0x00,0x00,0x00,0x00,0x00,0x0c]
+pfch 8199
+
+# CHECK-INST: pfch 20(%s11)
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x00,0x8b,0x00,0x0c]
+pfch 20(%s11)
+
+# CHECK-INST: pfch -1(, %s11)
+# CHECK-ENCODING: encoding: [0xff,0xff,0xff,0xff,0x8b,0x00,0x00,0x0c]
+pfch -1(, %s11)
+
+# CHECK-INST: pfch 20(%s10, %s11)
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x00,0x0c]
+pfch 20(%s10, %s11)
diff --git a/llvm/test/MC/VE/TS1AM.s b/llvm/test/MC/VE/TS1AM.s
new file mode 100644
index 000000000000..ff7e57efca30
--- /dev/null
+++ b/llvm/test/MC/VE/TS1AM.s
@@ -0,0 +1,16 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: ts1am.l %s20, 20(%s11), %s32
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0xa0,0x14,0x42]
+ts1am.l %s20, 20(%s11), %s32
+
+# CHECK-INST: ts1am.w %s20, 8192, 63
+# CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x00,0x3f,0x94,0x42]
+ts1am.w %s20, 8192, 63
+
+# CHECK-INST: ts1am.l %s20, 8192, 127
+# CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x00,0x7f,0x14,0x42]
+ts1am.l %s20, 8192, 127
diff --git a/llvm/test/MC/VE/TS2AM.s b/llvm/test/MC/VE/TS2AM.s
new file mode 100644
index 000000000000..dc402a313f67
--- /dev/null
+++ b/llvm/test/MC/VE/TS2AM.s
@@ -0,0 +1,12 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: ts2am %s20, 20(%s11), %s32
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0xa0,0x14,0x43]
+ts2am %s20, 20(%s11), %s32
+
+# CHECK-INST: ts2am %s20, 8192, 127
+# CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x00,0x7f,0x14,0x43]
+ts2am %s20, 8192, 127
diff --git a/llvm/test/MC/VE/TS3AM.s b/llvm/test/MC/VE/TS3AM.s
new file mode 100644
index 000000000000..cc0b509923ae
--- /dev/null
+++ b/llvm/test/MC/VE/TS3AM.s
@@ -0,0 +1,12 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: ts3am %s20, 20(%s11), %s32
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0xa0,0x14,0x52]
+ts3am %s20, 20(%s11), %s32
+
+# CHECK-INST: ts3am %s20, 8192, 1
+# CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x00,0x01,0x14,0x52]
+ts3am %s20, 8192, 1
More information about the llvm-commits
mailing list