[PATCH] D80127: [ARM][MachineOutliner] Add LR RegSave mode.

[Yvan Roux via Phabricator via llvm-commits]

yroux updated this revision to Diff 269460.
yroux added a comment.

Change register class to rGPR for both modes and updated testcase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80127/new/

https://reviews.llvm.org/D80127

Files:
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/test/CodeGen/ARM/machine-outliner-lr-regsave.mir

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