[llvm] f41994f - GlobalISel: Make it clearer that regbank/class are mutually exclusive

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-06-08T10:15:53-04:00
New Revision: f41994f85bf620be320339bd3f51f2f5fd200e8c

URL: https://github.com/llvm/llvm-project/commit/f41994f85bf620be320339bd3f51f2f5fd200e8c
DIFF: https://github.com/llvm/llvm-project/commit/f41994f85bf620be320339bd3f51f2f5fd200e8c.diff

LOG: GlobalISel: Make it clearer that regbank/class are mutually exclusive

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
index e258ffb5ae76..cd99bee08d0e 100644
--- a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
@@ -375,12 +375,14 @@ const GISelInstProfileBuilder &GISelInstProfileBuilder::addNodeIDMachineOperand(
     LLT Ty = MRI.getType(Reg);
     if (Ty.isValid())
       addNodeIDRegType(Ty);
-    auto *RB = MRI.getRegBankOrNull(Reg);
-    if (RB)
-      addNodeIDRegType(RB);
-    auto *RC = MRI.getRegClassOrNull(Reg);
-    if (RC)
-      addNodeIDRegType(RC);
+
+    if (const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(Reg)) {
+      if (const auto *RB = RCOrRB.dyn_cast<const RegisterBank *>())
+        addNodeIDRegType(RB);
+      else if (const auto *RC = RCOrRB.dyn_cast<const TargetRegisterClass *>())
+        addNodeIDRegType(RC);
+    }
+
     assert(!MO.isImplicit() && "Unhandled case");
   } else if (MO.isImm())
     ID.AddInteger(MO.getImm());