[PATCH] D81368: [SVE] Disable Global and Fast ISel at -O0 if the SVE feature is found

[David Sherwood via Phabricator via llvm-commits]

david-arm created this revision.
david-arm added a reviewer: sdesmalen.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, tschuett.
Herald added a reviewer: rengolin.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.

At the moment we use Global ISel by default at -O0, however it is
currently not capable of dealing with scalable vectors for two
reasons:

1. The register banks know nothing about SVE registers.
2. The LLT (Low Level Type) class knows nothing about scalable

vectors.

For now, the easiest way to avoid users hitting issues when using
the SVE ACLE is to disable Global ISel. In addition, we need to
also disable Fast ISel, since it doesn't just work for scalable
vectors at the moment either.

I've added a couple of RUN lines to existing SVE tests to ensure
we can compile at -O0.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81368

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
  llvm/test/CodeGen/AArch64/sve-intrinsics-ld1.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-st1.ll


Index: llvm/test/CodeGen/AArch64/sve-intrinsics-st1.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-intrinsics-st1.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-st1.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
 
 ;
 ; ST1B
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-ld1.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-intrinsics-ld1.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-ld1.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
 
 ;
 ; LD1B
Index: llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -309,7 +309,18 @@
   if (getOptLevel() <= EnableGlobalISelAtO &&
       TT.getArch() != Triple::aarch64_32 &&
       !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
-    setGlobalISel(true);
+
+    bool HasSVE = false;
+    SmallVector<StringRef, 6> Features;
+    FS.split(Features, ',');
+    for (StringRef Feature : Features) {
+      if (Feature == "+sve")
+        HasSVE = true;
+      else if (Feature == "-sve")
+        HasSVE = false;
+    }
+
+    setGlobalISel(!HasSVE);
     setGlobalISelAbort(GlobalISelAbortMode::Disable);
   }
 
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1283,6 +1283,8 @@
 FastISel *
 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
                                       const TargetLibraryInfo *libInfo) const {
+  if (Subtarget->hasSVE())
+    return nullptr;
   return AArch64::createFastISel(funcInfo, libInfo);
 }
 


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