[PATCH] D81360: [PowerPC] Fix RM operands for some instructions
Zhang Kang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 8 02:40:57 PDT 2020
ZhangKang updated this revision to Diff 269132.
ZhangKang added a comment.
Add a test case.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81360/new/
https://reviews.llvm.org/D81360
Files:
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/setrnd.ll
Index: llvm/test/CodeGen/PowerPC/setrnd.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/setrnd.ll
+++ llvm/test/CodeGen/PowerPC/setrnd.ll
@@ -15,12 +15,12 @@
ret double %0
; BEFORE-FINALIZE-ISEL: test_setrndi
-; BEFORE-FINALIZE-ISEL: SETRNDi 2, implicit-def dead $rm, implicit $rm
+; BEFORE-FINALIZE-ISEL: SETRNDi 2, implicit-def dead $rm
; AFTER-FINALIZE-ISEL: test_setrndi
; AFTER-FINALIZE-ISEL: MFFS implicit $rm
-; AFTER-FINALIZE-ISEL: MTFSB0 31, implicit-def $rm, implicit $rm
-; AFTER-FINALIZE-ISEL: MTFSB1 30, implicit-def $rm, implicit $rm
+; AFTER-FINALIZE-ISEL: MTFSB0 31, implicit-def $rm
+; AFTER-FINALIZE-ISEL: MTFSB1 30, implicit-def $rm
; CHECK-LABEL: @test_setrndi
; CHECK: # %bb.0:
@@ -36,7 +36,7 @@
ret double %0
; BEFORE-FINALIZE-ISEL: test_setrnd
-; BEFORE-FINALIZE-ISEL: SETRND killed %1, implicit-def dead $rm, implicit $rm
+; BEFORE-FINALIZE-ISEL: SETRND killed %1, implicit-def dead $rm
; AFTER-FINALIZE-ISEL: test_setrnd
; AFTER-FINALIZE-ISEL: MFFS implicit $rm
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1468,7 +1468,7 @@
}
// Set the float rounding mode.
-let Uses = [RM], Defs = [RM] in {
+let Defs = [RM] in {
def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND),
"#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>;
@@ -1523,11 +1523,12 @@
def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
"bc 4, $bi, $dst">;
- let isReturn = 1, Uses = [LR, RM] in
+ let isReturn = 1, Uses = [LR, RM] in {
def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
"bclr 12, $bi, 0", IIC_BrB, []>;
def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
"bclr 4, $bi, 0", IIC_BrB, []>;
+ }
}
let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
@@ -2871,7 +2872,7 @@
// The above pseudo gets expanded to make use of the following instructions
// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
-let Uses = [RM], Defs = [RM] in {
+let Defs = [RM] in {
def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
"mtfsb0 $FM", IIC_IntMTFSB0, []>,
PPC970_DGroup_Single, PPC970_Unit_FPU;
@@ -4270,22 +4271,26 @@
def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
"mcrfs $BF, $BFA", IIC_BrMCR>;
+let Defs = [RM] in {
def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
"mtfsfi $BF, $U, $W", IIC_IntMFFS>;
def MTFSFI_rec : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
"mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm;
+}
def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec crrc:$BF, i32imm:$U, 0)>;
let Predicates = [HasFPU] in {
+let Defs = [RM] in {
def MTFSF : XFLForm_1<63, 711, (outs),
(ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
"mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
def MTFSF_rec : XFLForm_1<63, 711, (outs),
(ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
"mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm;
+}
def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>;
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