[llvm] 385adc4 - [VE] Support shift operation instructions in MC layer
Simon Moll via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 8 01:19:52 PDT 2020
Author: Kazushi (Jam) Marukawa
Date: 2020-06-08T10:19:14+02:00
New Revision: 385adc4720d02359229f3baea4eb30761e039264
URL: https://github.com/llvm/llvm-project/commit/385adc4720d02359229f3baea4eb30761e039264
DIFF: https://github.com/llvm/llvm-project/commit/385adc4720d02359229f3baea4eb30761e039264.diff
LOG: [VE] Support shift operation instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
shift operation instructions. Also change asmparser to support UImm7
operand. And, add new SLD/SRD/SLA instructions also.
Differential Revision: https://reviews.llvm.org/D81324
Added:
llvm/test/MC/VE/SLA.s
llvm/test/MC/VE/SLD.s
llvm/test/MC/VE/SLL.s
llvm/test/MC/VE/SRA.s
llvm/test/MC/VE/SRD.s
llvm/test/MC/VE/SRL.s
Modified:
llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
llvm/lib/Target/VE/VEInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
index 628fce349068..0ee74a914cca 100644
--- a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
+++ b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
@@ -191,6 +191,17 @@ class VEOperand : public MCParsedAsmOperand {
bool isMEMri() const { return Kind == k_MemoryRegImm; }
bool isMEMzi() const { return Kind == k_MemoryZeroImm; }
bool isCCOp() const { return Kind == k_CCOp; }
+ bool isUImm7() {
+ if (!isImm())
+ return false;
+
+ // Constant case
+ if (const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
+ int64_t Value = ConstExpr->getValue();
+ return isUInt<7>(Value);
+ }
+ return false;
+ }
bool isSImm7() {
if (!isImm())
return false;
@@ -340,6 +351,10 @@ class VEOperand : public MCParsedAsmOperand {
addExpr(Inst, Expr);
}
+ void addUImm7Operands(MCInst &Inst, unsigned N) const {
+ addImmOperands(Inst, N);
+ }
+
void addSImm7Operands(MCInst &Inst, unsigned N) const {
addImmOperands(Inst, N);
}
diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td
index 4372a8014d7f..ac32a9286f10 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.td
+++ b/llvm/lib/Target/VE/VEInstrInfo.td
@@ -39,6 +39,10 @@ include "VEInstrFormats.td"
// e.g. 0.0 (0x00000000) or -2.0 (0xC0000000=(2)1).
//===----------------------------------------------------------------------===//
+def ULO7 : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(N->getZExtValue() & 0x7f,
+ SDLoc(N), MVT::i32);
+}]>;
def LO7 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(SignExtend32(N->getSExtValue(), 7),
SDLoc(N), MVT::i32);
@@ -117,8 +121,13 @@ def uimm6 : Operand<i32>, PatLeaf<(imm), [{
return isUInt<6>(N->getZExtValue()); }]>;
// uimm7 - Generic immediate value.
+def UImm7AsmOperand : AsmOperandClass {
+ let Name = "UImm7";
+}
def uimm7 : Operand<i32>, PatLeaf<(imm), [{
- return isUInt<7>(N->getZExtValue()); }]>;
+ return isUInt<7>(N->getZExtValue()); }], ULO7> {
+ let ParserMatchClass = UImm7AsmOperand;
+}
// simm7 - Generic immediate value.
def SImm7AsmOperand : AsmOperandClass {
@@ -493,6 +502,44 @@ multiclass RRIm<string opcStr, bits<8>opc,
[(set Ty:$sx, (OpNode (Ty mimm:$sz), (i32 uimm7:$sy)))]>;
}
+// Special RR multiclass for 128 bits shift left instruction.
+// e.g. SLD
+let Constraints = "$hi = $sx", DisableEncoding = "$hi", hasSideEffects = 0 in
+multiclass RRILDm<string opcStr, bits<8>opc,
+ RegisterClass RC, ValueType Ty,
+ SDPatternOperator OpNode = null_frag> {
+ def rrr : RR<opc, (outs RC:$sx), (ins RC:$hi, RC:$sz, I32:$sy),
+ !strconcat(opcStr, " $sx, $sz, $sy")>;
+ let cz = 0 in
+ def rmr : RR<opc, (outs RC:$sx), (ins RC:$hi, mimm:$sz, I32:$sy),
+ !strconcat(opcStr, " $sx, $sz, $sy")>;
+ let cy = 0 in
+ def rri : RR<opc, (outs RC:$sx), (ins RC:$hi, RC:$sz, uimm7:$sy),
+ !strconcat(opcStr, " $sx, $sz, $sy")>;
+ let cy = 0, cz = 0 in
+ def rmi : RR<opc, (outs RC:$sx), (ins RC:$hi, mimm:$sz, uimm7:$sy),
+ !strconcat(opcStr, " $sx, $sz, $sy")>;
+}
+
+// Special RR multiclass for 128 bits shift right instruction.
+// e.g. SRD
+let Constraints = "$low = $sx", DisableEncoding = "$low", hasSideEffects = 0 in
+multiclass RRIRDm<string opcStr, bits<8>opc,
+ RegisterClass RC, ValueType Ty,
+ SDPatternOperator OpNode = null_frag> {
+ def rrr : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$low, I32:$sy),
+ !strconcat(opcStr, " $sx, $sz, $sy")>;
+ let cz = 0 in
+ def mrr : RR<opc, (outs RC:$sx), (ins mimm:$sz, RC:$low, I32:$sy),
+ !strconcat(opcStr, " $sx, $sz, $sy")>;
+ let cy = 0 in
+ def rri : RR<opc, (outs RC:$sx), (ins RC:$sz, RC:$low, uimm7:$sy),
+ !strconcat(opcStr, " $sx, $sz, $sy")>;
+ let cy = 0, cz = 0 in
+ def mri : RR<opc, (outs RC:$sx), (ins mimm:$sz, RC:$low, uimm7:$sy),
+ !strconcat(opcStr, " $sx, $sz, $sy")>;
+}
+
// Generic RR multiclass with an argument.
// e.g. LDZ, PCNT, and BRV
let cy = 0, sy = 0, hasSideEffects = 0 in
@@ -947,17 +994,20 @@ def : MnemonicAlias<"cmov.s", "cmov.s.at">;
defm SLL : RRIm<"sll", 0x65, I64, i64, shl>;
// Section 8.6.2 - SLD (Shift Left Double)
+defm SLD : RRILDm<"sld", 0x64, I64, i64>;
// Section 8.6.3 - SRL (Shift Right Logical)
defm SRL : RRIm<"srl", 0x75, I64, i64, srl>;
// Section 8.6.4 - SRD (Shift Right Double)
+defm SRD : RRIRDm<"srd", 0x74, I64, i64>;
// Section 8.6.5 - SLA (Shift Left Arithmetic)
defm SLAWSX : RRIm<"sla.w.sx", 0x66, I32, i32, shl>;
let cx = 1 in defm SLAWZX : RRIm<"sla.w.zx", 0x66, I32, i32>;
// Section 8.6.6 - SLAX (Shift Left Arithmetic)
+defm SLAL : RRIm<"sla.l", 0x57, I64, i64>;
// Section 8.6.7 - SRA (Shift Right Arithmetic)
defm SRAWSX : RRIm<"sra.w.sx", 0x76, I32, i32, sra>;
diff --git a/llvm/test/MC/VE/SLA.s b/llvm/test/MC/VE/SLA.s
new file mode 100644
index 000000000000..3f5708a8e1aa
--- /dev/null
+++ b/llvm/test/MC/VE/SLA.s
@@ -0,0 +1,28 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: sla.w.sx %s11, %s11, %s11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x66]
+sla.w.sx %s11, %s11, %s11
+
+# CHECK-INST: sla.w.zx %s11, %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x8b,0x66]
+sla.w.zx %s11, %s11, 63
+
+# CHECK-INST: sla.l %s11, %s11, 127
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x57]
+sla.l %s11, %s11, 127
+
+# CHECK-INST: sla.w.sx %s11, %s11, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x66]
+sla.w.sx %s11, %s11, 64
+
+# CHECK-INST: sla.w.zx %s11, (32)1, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x8b,0x66]
+sla.w.zx %s11, (32)1, 64
+
+# CHECK-INST: sla.l %s11, (32)0, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x57]
+sla.l %s11, (32)0, 63
diff --git a/llvm/test/MC/VE/SLD.s b/llvm/test/MC/VE/SLD.s
new file mode 100644
index 000000000000..17c5ac7d651b
--- /dev/null
+++ b/llvm/test/MC/VE/SLD.s
@@ -0,0 +1,28 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: sld %s11, %s11, %s11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x64]
+sld %s11, %s11, %s11
+
+# CHECK-INST: sld %s11, %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x0b,0x64]
+sld %s11, %s11, 63
+
+# CHECK-INST: sld %s11, %s11, 127
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x64]
+sld %s11, %s11, 127
+
+# CHECK-INST: sld %s11, %s11, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x64]
+sld %s11, %s11, 64
+
+# CHECK-INST: sld %s11, (32)1, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x0b,0x64]
+sld %s11, (32)1, 64
+
+# CHECK-INST: sld %s11, (32)0, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x64]
+sld %s11, (32)0, 63
diff --git a/llvm/test/MC/VE/SLL.s b/llvm/test/MC/VE/SLL.s
new file mode 100644
index 000000000000..19ce2c58b98c
--- /dev/null
+++ b/llvm/test/MC/VE/SLL.s
@@ -0,0 +1,28 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: sll %s11, %s11, %s11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x65]
+sll %s11, %s11, %s11
+
+# CHECK-INST: sll %s11, %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x0b,0x65]
+sll %s11, %s11, 63
+
+# CHECK-INST: sll %s11, %s11, 127
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x65]
+sll %s11, %s11, 127
+
+# CHECK-INST: sll %s11, %s11, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x65]
+sll %s11, %s11, 64
+
+# CHECK-INST: sll %s11, (32)1, 35
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x23,0x0b,0x65]
+sll %s11, (32)1, 35
+
+# CHECK-INST: sll %s11, (32)0, 23
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x17,0x0b,0x65]
+sll %s11, (32)0, 23
diff --git a/llvm/test/MC/VE/SRA.s b/llvm/test/MC/VE/SRA.s
new file mode 100644
index 000000000000..51970e349516
--- /dev/null
+++ b/llvm/test/MC/VE/SRA.s
@@ -0,0 +1,28 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: sra.w.sx %s11, %s11, %s11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x76]
+sra.w.sx %s11, %s11, %s11
+
+# CHECK-INST: sra.w.zx %s11, %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x8b,0x76]
+sra.w.zx %s11, %s11, 63
+
+# CHECK-INST: sra.l %s11, %s11, 127
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x77]
+sra.l %s11, %s11, 127
+
+# CHECK-INST: sra.w.sx %s11, %s11, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x76]
+sra.w.sx %s11, %s11, 64
+
+# CHECK-INST: sra.w.zx %s11, (32)1, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x8b,0x76]
+sra.w.zx %s11, (32)1, 64
+
+# CHECK-INST: sra.l %s11, (32)0, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x77]
+sra.l %s11, (32)0, 63
diff --git a/llvm/test/MC/VE/SRD.s b/llvm/test/MC/VE/SRD.s
new file mode 100644
index 000000000000..e66dcf7a4bfa
--- /dev/null
+++ b/llvm/test/MC/VE/SRD.s
@@ -0,0 +1,28 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: srd %s11, %s11, %s11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x74]
+srd %s11, %s11, %s11
+
+# CHECK-INST: srd %s11, %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x0b,0x74]
+srd %s11, %s11, 63
+
+# CHECK-INST: srd %s11, %s11, 127
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x74]
+srd %s11, %s11, 127
+
+# CHECK-INST: srd %s11, %s11, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x74]
+srd %s11, %s11, 64
+
+# CHECK-INST: srd %s11, (32)1, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x0b,0x74]
+srd %s11, (32)1, 64
+
+# CHECK-INST: srd %s11, (32)0, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x74]
+srd %s11, (32)0, 63
diff --git a/llvm/test/MC/VE/SRL.s b/llvm/test/MC/VE/SRL.s
new file mode 100644
index 000000000000..58840b9bc7cc
--- /dev/null
+++ b/llvm/test/MC/VE/SRL.s
@@ -0,0 +1,28 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN: | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: srl %s11, %s11, %s11
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x75]
+srl %s11, %s11, %s11
+
+# CHECK-INST: srl %s11, %s11, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x0b,0x75]
+srl %s11, %s11, 63
+
+# CHECK-INST: srl %s11, %s11, 127
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x75]
+srl %s11, %s11, 127
+
+# CHECK-INST: srl %s11, %s11, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x75]
+srl %s11, %s11, 64
+
+# CHECK-INST: srl %s11, (32)1, 64
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x0b,0x75]
+srl %s11, (32)1, 64
+
+# CHECK-INST: srl %s11, (32)0, 63
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x75]
+srl %s11, (32)0, 63
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