[PATCH] D81343: [AArch64] custom lowering for i128 popcount

[Shawn Landden via Phabricator via llvm-commits]

shawnl marked an inline comment as done.
shawnl added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/popcount.ll:10
+; CHECK-NEXT:    add x8, x0, #8 // =8
+; CHECK-NEXT:    ld1 { v0.d }[1], [x8]
+; CHECK-NEXT:    cnt v0.16b, v0.16b
----------------
shawnl wrote:
> efriedma wrote:
> > Why are we generating two loads here?  Something related to the BITCAST legalization?
> Yes, it should be:
> 
> > ldr q0, [x0]
> 
> 
Yes, it is going to AArch64ISelLowering.cpp:14006


```
  case ISD::LOAD: {
    assert(SDValue(N, 0).getValueType() == MVT::i128 &&
           "unexpected load's value type");
    LoadSDNode *LoadNode = cast<LoadSDNode>(N);
    if (!LoadNode->isVolatile() || LoadNode->getMemoryVT() != MVT::i128) {
      // Non-volatile loads are optimized later in AArch64's load/store
      // optimizer.    // <======This is not happening
      return; 
    }

    SDValue Result = DAG.getMemIntrinsicNode(
        AArch64ISD::LDP, SDLoc(N),
        DAG.getVTList({MVT::i64, MVT::i64, MVT::Other}),
        {LoadNode->getChain(), LoadNode->getBasePtr()}, LoadNode->getMemoryVT(),
        LoadNode->getMemOperand());

    SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128,
                               Result.getValue(0), Result.getValue(1));
    Results.append({Pair, Result.getValue(2) /* Chain */});
    return;
  }
```


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D81343