[PATCH] D81307: [X86] Return 0 from TTI getNumberOfRegisters and getRegisterBitWidth on SSE1 only targets

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

Add a minimal test for SLP to make sure this is happening? Might be able to just add a RUN line to some existing test file.



================
Comment at: llvm/lib/Target/X86/X86TargetTransformInfo.cpp:121
   bool Vector = (ClassID == 1);
-  if (Vector && !ST->hasSSE1())
+  // SSE2 is required for integer vectors limiting usefulness with SSE1.
+  if (Vector && !ST->hasSSE2())
----------------
I'd word this differently to make it clearer:
  // Avoid auto-vectorizing when compiling for SSE1 only. 
  // That forces codegen to undo integer and v2f64 vectorization.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81307/new/

https://reviews.llvm.org/D81307