[llvm] bd67d68 - [X86][SSE] Add MOVMSK tests where we're using a more narrow vector elements than necessary

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-06-07T10:48:11+01:00
New Revision: bd67d68ca1ddb0f857f39761a061eed45072718a

URL: https://github.com/llvm/llvm-project/commit/bd67d68ca1ddb0f857f39761a061eed45072718a
DIFF: https://github.com/llvm/llvm-project/commit/bd67d68ca1ddb0f857f39761a061eed45072718a.diff

LOG: [X86][SSE] Add MOVMSK tests where we're using a more narrow vector elements than necessary

First step towards fixing PR37087

Added: 
    llvm/test/CodeGen/X86/combine-movmsk.ll

Modified: 
    llvm/test/CodeGen/X86/combine-movmsk-avx.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/combine-movmsk-avx.ll b/llvm/test/CodeGen/X86/combine-movmsk-avx.ll
index 0de723e287c6..5b1d5a3b8ed2 100644
--- a/llvm/test/CodeGen/X86/combine-movmsk-avx.ll
+++ b/llvm/test/CodeGen/X86/combine-movmsk-avx.ll
@@ -5,6 +5,26 @@
 declare i32 @llvm.x86.avx.movmsk.pd.256(<4 x double>)
 declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>)
 
+; TODO - Use widest possible vector for movmsk comparisons
+
+define i1 @movmskps_bitcast_v4f64(<4 x double> %a0) {
+; CHECK-LABEL: movmskps_bitcast_v4f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vxorpd %xmm1, %xmm1, %xmm1
+; CHECK-NEXT:    vcmpeqpd %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    vmovmskps %ymm0, %eax
+; CHECK-NEXT:    testl %eax, %eax
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+  %1 = fcmp oeq <4 x double> %a0, zeroinitializer
+  %2 = sext <4 x i1> %1 to <4 x i64>
+  %3 = bitcast <4 x i64> %2 to <8 x float>
+  %4 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %3)
+  %5 = icmp eq i32 %4, 0
+  ret i1 %5
+}
+
 ;
 ; TODO - Avoid sign extension ops when just extracting the sign bits.
 ;

diff  --git a/llvm/test/CodeGen/X86/combine-movmsk.ll b/llvm/test/CodeGen/X86/combine-movmsk.ll
new file mode 100644
index 000000000000..dff939ae1ef6
--- /dev/null
+++ b/llvm/test/CodeGen/X86/combine-movmsk.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
+
+declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>)
+declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>)
+declare i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8>)
+
+; TODO - Use widest possible vector for movmsk comparisons
+
+define i1 @movmskps_bitcast_v2f64(<2 x double> %a0) {
+; SSE-LABEL: movmskps_bitcast_v2f64:
+; SSE:       # %bb.0:
+; SSE-NEXT:    xorpd %xmm1, %xmm1
+; SSE-NEXT:    cmpeqpd %xmm0, %xmm1
+; SSE-NEXT:    movmskps %xmm1, %eax
+; SSE-NEXT:    testl %eax, %eax
+; SSE-NEXT:    sete %al
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: movmskps_bitcast_v2f64:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vxorpd %xmm1, %xmm1, %xmm1
+; AVX-NEXT:    vcmpeqpd %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    vmovmskps %xmm0, %eax
+; AVX-NEXT:    testl %eax, %eax
+; AVX-NEXT:    sete %al
+; AVX-NEXT:    retq
+  %1 = fcmp oeq <2 x double> zeroinitializer, %a0
+  %2 = sext <2 x i1> %1 to <2 x i64>
+  %3 = bitcast <2 x i64> %2 to <4 x float>
+  %4 = tail call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %3)
+  %5 = icmp eq i32 %4, 0
+  ret i1 %5
+}
+
+define i1 @movmskps_bitcast_v2i64(<2 x i64> %a0) {
+; SSE2-LABEL: movmskps_bitcast_v2i64:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    pxor %xmm1, %xmm1
+; SSE2-NEXT:    pcmpgtd %xmm0, %xmm1
+; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
+; SSE2-NEXT:    pmovmskb %xmm0, %eax
+; SSE2-NEXT:    testl %eax, %eax
+; SSE2-NEXT:    sete %al
+; SSE2-NEXT:    retq
+;
+; SSE42-LABEL: movmskps_bitcast_v2i64:
+; SSE42:       # %bb.0:
+; SSE42-NEXT:    pxor %xmm1, %xmm1
+; SSE42-NEXT:    pcmpgtq %xmm0, %xmm1
+; SSE42-NEXT:    pmovmskb %xmm1, %eax
+; SSE42-NEXT:    testl %eax, %eax
+; SSE42-NEXT:    sete %al
+; SSE42-NEXT:    retq
+;
+; AVX-LABEL: movmskps_bitcast_v2i64:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    vpmovmskb %xmm0, %eax
+; AVX-NEXT:    testl %eax, %eax
+; AVX-NEXT:    sete %al
+; AVX-NEXT:    retq
+  %1 = icmp sgt <2 x i64> zeroinitializer, %a0
+  %2 = sext <2 x i1> %1 to <2 x i64>
+  %3 = bitcast <2 x i64> %2 to <16 x i8>
+  %4 = tail call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %3)
+  %5 = icmp eq i32 %4, 0
+  ret i1 %5
+}
+
+define i1 @movmskps_bitcast_v4f32(<4 x float> %a0) {
+; SSE-LABEL: movmskps_bitcast_v4f32:
+; SSE:       # %bb.0:
+; SSE-NEXT:    xorps %xmm1, %xmm1
+; SSE-NEXT:    cmpeqps %xmm0, %xmm1
+; SSE-NEXT:    pmovmskb %xmm1, %eax
+; SSE-NEXT:    testl %eax, %eax
+; SSE-NEXT:    sete %al
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: movmskps_bitcast_v4f32:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
+; AVX-NEXT:    vcmpeqps %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpmovmskb %xmm0, %eax
+; AVX-NEXT:    testl %eax, %eax
+; AVX-NEXT:    sete %al
+; AVX-NEXT:    retq
+  %1 = fcmp oeq <4 x float> %a0, zeroinitializer
+  %2 = sext <4 x i1> %1 to <4 x i32>
+  %3 = bitcast <4 x i32> %2 to <16 x i8>
+  %4 = tail call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %3)
+  %5 = icmp eq i32 %4, 0
+  ret i1 %5
+}