[PATCH] D81275: [AMDGPU] Move default initialization of M0 register after the instruction selection

[Valery Pykhtin via Phabricator via llvm-commits]

vpykhtin marked 2 inline comments as done.
vpykhtin added a comment.

The SI_INIT_M0 is still used for instructions that I mention in hasNonDefaultM0. Comments say it was introduced to produce S_MOV_B32 m0 so the CSE could join them.

There're a few instructions that set M0 out of intrinsic arguments like V_INTERP, they produce COPY to M0.



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Comment at: llvm/lib/Target/AMDGPU/DSInstructions.td:55
+  // initialize M0 in SITargetLowering::AdjustInstrPostInstrSelection
+  let hasPostISelHook = has_m0_read;
 }
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arsenm wrote:
> Could you just set hasPostISelHook to 0 for the special cases?
I thought to do it this way, the hook is also used for converting to no-ret atomics, I need to check if there is a case for atomic but not for default M0 init. 


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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:10792
+// see AMDGPUDAGToDAGISel::glueCopyToM0, SITargetLowering::copyToM0 usage
+static bool hasNonDefaultM0(unsigned Opcode) {
+  switch(Opcode) {
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arsenm wrote:
> You could just use this in an assert if you disabled the post isel hook for the special cases
need to check with intersection on no-ret atomics.


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https://reviews.llvm.org/D81275