[PATCH] D81224: [AMDGPU] Fix failure in VCC spilling

[Carl Ritson via Phabricator via llvm-commits]

critson marked 3 inline comments as done.
critson added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:939
+            getMatchingSuperReg(getSubReg(SuperReg, SplitParts[FirstPart]),
+                                AMDGPU::sub0, &AMDGPU::SGPR_64RegClass);
+      }
----------------
arsenm wrote:
> Don't you just need to change SGPR_64RegClass to SReg_64RegClass (or maybe the XEXEC variant?)
Thanks, that is a better solution.


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Comment at: llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir:2
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=CHECK %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=CHECK %s
+
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arsenm wrote:
> -mattr=-wavefrontsize32,+wavefrontsize64 is unnecessary since wave32 is the default
This is setting wave64 as the test is not intended for wave32.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D81224/new/

https://reviews.llvm.org/D81224