[llvm] 22c4c6d - [PhaseOrdering] add tests for reductions; NFC (PR43953)
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 5 09:39:17 PDT 2020
Author: Sanjay Patel
Date: 2020-06-05T12:38:49-04:00
New Revision: 22c4c6dd382cad8e87dc2fc8494307b0b0914e80
URL: https://github.com/llvm/llvm-project/commit/22c4c6dd382cad8e87dc2fc8494307b0b0914e80
DIFF: https://github.com/llvm/llvm-project/commit/22c4c6dd382cad8e87dc2fc8494307b0b0914e80.diff
LOG: [PhaseOrdering] add tests for reductions; NFC (PR43953)
Added:
Modified:
llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
index 304b38b09bce..aa59c24c3737 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
@@ -63,3 +63,246 @@ define i32 @ext_ext_partial_add_reduction_and_extra_add_v4i32(<4 x i32> %x, <4 x
%x2y210 = add i32 %x2, %y210
ret i32 %x2y210
}
+
+; PR43953 - https://bugs.llvm.org/show_bug.cgi?id=43953
+; We want to end up with a single reduction on the next 4 tests.
+
+define i32 @TestVectorsEqual(i32* noalias %Vec0, i32* noalias %Vec1, i32 %Tolerance) {
+; CHECK-LABEL: @TestVectorsEqual(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[VEC0:%.*]] to <4 x i32>*
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32* [[VEC1:%.*]] to <4 x i32>*
+; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = sub nsw <4 x i32> [[TMP1]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = icmp slt <4 x i32> [[TMP4]], zeroinitializer
+; CHECK-NEXT: [[TMP6:%.*]] = sub nsw <4 x i32> zeroinitializer, [[TMP4]]
+; CHECK-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> [[TMP6]], <4 x i32> [[TMP4]]
+; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x i32> [[TMP7]], <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP7]], [[RDX_SHUF]]
+; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x i32> [[BIN_RDX]], <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT: [[BIN_RDX4:%.*]] = add <4 x i32> [[BIN_RDX]], [[RDX_SHUF3]]
+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[BIN_RDX4]], i32 0
+; CHECK-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP8]], [[TOLERANCE:%.*]]
+; CHECK-NEXT: [[COND6:%.*]] = zext i1 [[CMP5]] to i32
+; CHECK-NEXT: ret i32 [[COND6]]
+;
+entry:
+ br label %for.cond
+
+for.cond:
+ %sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ]
+ %Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
+ %cmp = icmp slt i32 %Component.0, 4
+ br i1 %cmp, label %for.body, label %for.cond.cleanup
+
+for.cond.cleanup:
+ br label %for.end
+
+for.body:
+ %idxprom = sext i32 %Component.0 to i64
+ %arrayidx = getelementptr inbounds i32, i32* %Vec0, i64 %idxprom
+ %0 = load i32, i32* %arrayidx, align 4
+ %idxprom1 = sext i32 %Component.0 to i64
+ %arrayidx2 = getelementptr inbounds i32, i32* %Vec1, i64 %idxprom1
+ %1 = load i32, i32* %arrayidx2, align 4
+ %sub = sub nsw i32 %0, %1
+ %cmp3 = icmp sge i32 %sub, 0
+ br i1 %cmp3, label %cond.true, label %cond.false
+
+cond.true:
+ br label %cond.end
+
+cond.false:
+ %sub4 = sub nsw i32 0, %sub
+ br label %cond.end
+
+cond.end:
+ %cond = phi i32 [ %sub, %cond.true ], [ %sub4, %cond.false ]
+ %add = add nsw i32 %sum.0, %cond
+ br label %for.inc
+
+for.inc:
+ %inc = add nsw i32 %Component.0, 1
+ br label %for.cond
+
+for.end:
+ %cmp5 = icmp sle i32 %sum.0, %Tolerance
+ %2 = zext i1 %cmp5 to i64
+ %cond6 = select i1 %cmp5, i32 1, i32 0
+ ret i32 %cond6
+}
+
+define i32 @TestVectorsEqual_alt(i32* noalias %Vec0, i32* noalias %Vec1, i32 %Tolerance) {
+; CHECK-LABEL: @TestVectorsEqual_alt(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[VEC0:%.*]] to <4 x i32>*
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32* [[VEC1:%.*]] to <4 x i32>*
+; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4
+; CHECK-NEXT: [[RDX_SHUF5:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
+; CHECK-NEXT: [[BIN_RDX6:%.*]] = add <4 x i32> [[TMP1]], [[RDX_SHUF5]]
+; CHECK-NEXT: [[RDX_SHUF7:%.*]] = shufflevector <4 x i32> [[BIN_RDX6]], <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT: [[BIN_RDX8:%.*]] = add <4 x i32> [[BIN_RDX6]], [[RDX_SHUF7]]
+; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP3]], [[RDX_SHUF]]
+; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x i32> [[BIN_RDX]], <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT: [[BIN_RDX4:%.*]] = add <4 x i32> [[BIN_RDX]], [[RDX_SHUF3]]
+; CHECK-NEXT: [[TMP4:%.*]] = sub <4 x i32> [[BIN_RDX8]], [[BIN_RDX4]]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP4]], i32 0
+; CHECK-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP5]], [[TOLERANCE:%.*]]
+; CHECK-NEXT: [[COND:%.*]] = zext i1 [[CMP3]] to i32
+; CHECK-NEXT: ret i32 [[COND]]
+;
+entry:
+ br label %for.cond
+
+for.cond:
+ %sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ]
+ %Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
+ %cmp = icmp slt i32 %Component.0, 4
+ br i1 %cmp, label %for.body, label %for.cond.cleanup
+
+for.cond.cleanup:
+ br label %for.end
+
+for.body:
+ %idxprom = sext i32 %Component.0 to i64
+ %arrayidx = getelementptr inbounds i32, i32* %Vec0, i64 %idxprom
+ %0 = load i32, i32* %arrayidx, align 4
+ %idxprom1 = sext i32 %Component.0 to i64
+ %arrayidx2 = getelementptr inbounds i32, i32* %Vec1, i64 %idxprom1
+ %1 = load i32, i32* %arrayidx2, align 4
+ %sub = sub i32 %0, %1
+ %add = add i32 %sum.0, %sub
+ br label %for.inc
+
+for.inc:
+ %inc = add nsw i32 %Component.0, 1
+ br label %for.cond
+
+for.end:
+ %cmp3 = icmp ule i32 %sum.0, %Tolerance
+ %2 = zext i1 %cmp3 to i64
+ %cond = select i1 %cmp3, i32 1, i32 0
+ ret i32 %cond
+}
+
+define i32 @TestVectorsEqualFP(float* noalias %Vec0, float* noalias %Vec1, float %Tolerance) {
+; CHECK-LABEL: @TestVectorsEqualFP(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[VEC0:%.*]] to <4 x float>*
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[VEC1:%.*]] to <4 x float>*
+; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, <4 x float>* [[TMP2]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = fsub fast <4 x float> [[TMP1]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP4]])
+; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
+; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd fast <4 x float> [[TMP5]], [[RDX_SHUF]]
+; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT: [[BIN_RDX4:%.*]] = fadd fast <4 x float> [[BIN_RDX]], [[RDX_SHUF3]]
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[BIN_RDX4]], i32 0
+; CHECK-NEXT: [[CMP4:%.*]] = fcmp fast ole float [[TMP6]], [[TOLERANCE:%.*]]
+; CHECK-NEXT: [[COND5:%.*]] = zext i1 [[CMP4]] to i32
+; CHECK-NEXT: ret i32 [[COND5]]
+;
+entry:
+ br label %for.cond
+
+for.cond:
+ %sum.0 = phi float [ 0.000000e+00, %entry ], [ %add, %for.inc ]
+ %Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
+ %cmp = icmp slt i32 %Component.0, 4
+ br i1 %cmp, label %for.body, label %for.cond.cleanup
+
+for.cond.cleanup:
+ br label %for.end
+
+for.body:
+ %idxprom = sext i32 %Component.0 to i64
+ %arrayidx = getelementptr inbounds float, float* %Vec0, i64 %idxprom
+ %0 = load float, float* %arrayidx, align 4
+ %idxprom1 = sext i32 %Component.0 to i64
+ %arrayidx2 = getelementptr inbounds float, float* %Vec1, i64 %idxprom1
+ %1 = load float, float* %arrayidx2, align 4
+ %sub = fsub fast float %0, %1
+ %cmp3 = fcmp fast oge float %sub, 0.000000e+00
+ br i1 %cmp3, label %cond.true, label %cond.false
+
+cond.true:
+ br label %cond.end
+
+cond.false:
+ %fneg = fneg fast float %sub
+ br label %cond.end
+
+cond.end:
+ %cond = phi fast float [ %sub, %cond.true ], [ %fneg, %cond.false ]
+ %add = fadd fast float %sum.0, %cond
+ br label %for.inc
+
+for.inc:
+ %inc = add nsw i32 %Component.0, 1
+ br label %for.cond
+
+for.end:
+ %cmp4 = fcmp fast ole float %sum.0, %Tolerance
+ %2 = zext i1 %cmp4 to i64
+ %cond5 = select i1 %cmp4, i32 1, i32 0
+ ret i32 %cond5
+}
+
+define i32 @TestVectorsEqualFP_alt(float* noalias %Vec0, float* noalias %Vec1, float %Tolerance) {
+; CHECK-LABEL: @TestVectorsEqualFP_alt(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[VEC0:%.*]] to <4 x float>*
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[VEC1:%.*]] to <4 x float>*
+; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, <4 x float>* [[TMP2]], align 4
+; CHECK-NEXT: [[RDX_SHUF5:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
+; CHECK-NEXT: [[BIN_RDX6:%.*]] = fadd fast <4 x float> [[TMP1]], [[RDX_SHUF5]]
+; CHECK-NEXT: [[RDX_SHUF7:%.*]] = shufflevector <4 x float> [[BIN_RDX6]], <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT: [[BIN_RDX8:%.*]] = fadd fast <4 x float> [[BIN_RDX6]], [[RDX_SHUF7]]
+; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[TMP3]], <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
+; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd fast <4 x float> [[TMP3]], [[RDX_SHUF]]
+; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT: [[BIN_RDX4:%.*]] = fadd fast <4 x float> [[BIN_RDX]], [[RDX_SHUF3]]
+; CHECK-NEXT: [[TMP4:%.*]] = fsub fast <4 x float> [[BIN_RDX8]], [[BIN_RDX4]]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP4]], i32 0
+; CHECK-NEXT: [[CMP3:%.*]] = fcmp fast ole float [[TMP5]], [[TOLERANCE:%.*]]
+; CHECK-NEXT: [[COND:%.*]] = zext i1 [[CMP3]] to i32
+; CHECK-NEXT: ret i32 [[COND]]
+;
+entry:
+ br label %for.cond
+
+for.cond:
+ %sum.0 = phi float [ 0.000000e+00, %entry ], [ %add, %for.inc ]
+ %Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
+ %cmp = icmp slt i32 %Component.0, 4
+ br i1 %cmp, label %for.body, label %for.cond.cleanup
+
+for.cond.cleanup:
+ br label %for.end
+
+for.body:
+ %idxprom = sext i32 %Component.0 to i64
+ %arrayidx = getelementptr inbounds float, float* %Vec0, i64 %idxprom
+ %0 = load float, float* %arrayidx, align 4
+ %idxprom1 = sext i32 %Component.0 to i64
+ %arrayidx2 = getelementptr inbounds float, float* %Vec1, i64 %idxprom1
+ %1 = load float, float* %arrayidx2, align 4
+ %sub = fsub fast float %0, %1
+ %add = fadd fast float %sum.0, %sub
+ br label %for.inc
+
+for.inc:
+ %inc = add nsw i32 %Component.0, 1
+ br label %for.cond
+
+for.end:
+ %cmp3 = fcmp fast ole float %sum.0, %Tolerance
+ %2 = zext i1 %cmp3 to i64
+ %cond = select i1 %cmp3, i32 1, i32 0
+ ret i32 %cond
+}
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