[llvm] bca413b - Fix a typo in AMDGPU docs

[via llvm-commits]

Author: madhur13490
Date: 2020-06-05T13:30:17Z
New Revision: bca413b036bfce553a2d245e6783fc59a9994105

URL: https://github.com/llvm/llvm-project/commit/bca413b036bfce553a2d245e6783fc59a9994105
DIFF: https://github.com/llvm/llvm-project/commit/bca413b036bfce553a2d245e6783fc59a9994105.diff

LOG: Fix a typo in AMDGPU docs

Reviewers: t-tye, arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81247

Added: 
    

Modified: 
    llvm/docs/AMDGPUUsage.rst

Removed: 
    


################################################################################
diff  --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 69c7f88f945e..46c2297482c2 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -3851,7 +3851,7 @@ The setting of registers is done by GPU CP/ADC/SPI hardware as follows:
 4. The VGPRs are set by SPI which only supports specifying either (X), (X, Y)
    or (X, Y, Z).
 
-Flat Scratch register pair are adjacent SGRRs so they can be moved as a 64-bit
+Flat Scratch register pair are adjacent SGPRs so they can be moved as a 64-bit
 value to the hardware required SGPRn-3 and SGPRn-4 respectively.
 
 The global segment can be accessed either using buffer instructions (GFX6 which