[PATCH] D81214: [RISCV] Add vector instructions for FPR64.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai created this revision.
HsiangKai added reviewers: evandro, rogfer01, rkruppe.
Herald added subscribers: luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
Herald added a project: LLVM.

For ".vf" instructions, there is a floating point scalar argument for the operations. If the scalar type of the argument is f64, we need to assign FPR64 for it.

In this patch, I add "CodeGenOnly" instructions for the FPR64 version of the instructions. For example, there are two instructions for vfadd.vf. One is VFADD_VF for FPR32 and the other is VFADD_VD for FPR64.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81214

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td


Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -232,15 +232,17 @@
 }
 
 // op vd, vs2, rs1, vm (Float)
-class VALUVF<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class VALUVF<bits<6> funct6, RISCVVFormat opv, string opcodestr,
+             RegisterClass ScalarOp = FPR32>
     : RVInstVX<funct6, opv, (outs VRegOp:$vd),
-                (ins VRegOp:$vs2, FPR32:$rs1, VMaskOp:$vm),
+                (ins VRegOp:$vs2, ScalarOp:$rs1, VMaskOp:$vm),
                 opcodestr, "$vd, $vs2, $rs1$vm">;
 
 // op vd, rs1, vs2, vm (Float) (with mask, reverse the order of rs1 and vs2)
-class VALUrVF<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+class VALUrVF<bits<6> funct6, RISCVVFormat opv, string opcodestr,
+              RegisterClass ScalarOp = FPR32>
     : RVInstVX<funct6, opv, (outs VRegOp:$vd),
-                (ins FPR32:$rs1, VRegOp:$vs2, VMaskOp:$vm),
+                (ins ScalarOp:$rs1, VRegOp:$vs2, VMaskOp:$vm),
                 opcodestr, "$vd, $rs1, $vs2$vm">;
 
 // op vd, vs2, vm (use vs1 as instruction encoding)
@@ -338,15 +340,24 @@
 multiclass VALU_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> {
   def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">;
   def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">;
+  let isCodeGenOnly = 1 in {
+  def D : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f", FPR64>;
+  }
 }
 
 multiclass VALU_FV_F<string opcodestr, bits<6> funct6, string vw = "v"> {
   def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">;
+  let isCodeGenOnly = 1 in {
+  def D : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f", FPR64>;
+  }
 }
 
 multiclass VALUr_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> {
   def V : VALUrVV<funct6, OPFVV, opcodestr # "." # vw # "v">;
   def F : VALUrVF<funct6, OPFVF, opcodestr # "." # vw # "f">;
+  let isCodeGenOnly = 1 in {
+  def D : VALUrVF<funct6, OPFVF, opcodestr # "." # vw # "f", FPR64>;
+  }
 }
 
 multiclass VALU_FV_V<string opcodestr, bits<6> funct6> {
@@ -716,6 +727,13 @@
                            "vfmerge.vfm", "$vd, $vs2, $rs1, v0"> {
   let vm = 0;
 }
+let isCodeGenOnly = 1 in {
+def VFMERGE_VDM : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd),
+                           (ins VRegOp:$vs2, FPR64:$rs1, VMV0:$v0),
+                           "vfmerge.vfm", "$vd, $vs2, $rs1, v0"> {
+  let vm = 0;
+}
+}
 
 // Vector Floating-Point Move Instruction
 def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd),
@@ -723,6 +741,13 @@
   let vs2 = 0;
   let vm = 1;
 }
+let isCodeGenOnly = 1 in {
+def VFMV_V_D : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd),
+                       (ins FPR64:$rs1), "vfmv.v.f", "$vd, $rs1"> {
+  let vs2 = 0;
+  let vm = 1;
+}
+}
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
 // Single-Width Floating-Point/Integer Type-Convert Instructions
@@ -860,7 +885,12 @@
                       (ins VRegOp:$vs2), "vfmv.f.s", "$vd, $vs2">;
 def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VRegOp:$vd),
                       (ins FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">;
-
+let isCodeGenOnly = 1 in {
+def VFMV_D_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR64:$vd),
+                      (ins VRegOp:$vs2), "vfmv.f.s", "$vd, $vs2">;
+def VFMV_S_D : RVInstV2<0b010000, 0b00000, OPFVF, (outs VRegOp:$vd),
+                      (ins FPR64:$rs1), "vfmv.s.f", "$vd, $rs1">;
+}
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1
 
 // Vector Slide Instructions


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