[PATCH] D81182: [AArch64][GlobalISel] Select trn1 and trn2

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
paquette added a reviewer: aemerson.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka.
Herald added a project: LLVM.

Same idea as for zip, uzp, etc. Teach the post-legalizer combiner to recognize G_SHUFFLE_VECTORs that are trn1/trn2 instructions.

- Add G_TRN1 and G_TRN2
- Port mask matching code from AArch64ISelLowering
- Produce G_TRN1 and G_TRN2 in the post-legalizer combiner
- Select via importer

Add select-trn.mir to test selection.

Add postlegalizer-combiner-trn.mir to test the combine. This is similar to the existing arm64-trn test.

Note that both of these tests contain things we currently don't legalize.

I figured it would be easier to test these now rather than later, since once we legalize the G_SHUFFLE_VECTORs, it's not guaranteed that someone will update the tests.


https://reviews.llvm.org/D81182

Files:
  llvm/lib/Target/AArch64/AArch64Combine.td
  llvm/lib/Target/AArch64/AArch64InstrGISel.td
  llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-trn.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-trn.mir

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