[PATCH] D80867: [x86] form reduction intrinsics over raw IR

[Sanjay Patel via Phabricator via llvm-commits]

spatel updated this revision to Diff 268531.
spatel retitled this revision from "[x86][WIP] form reduction intrinsics over raw IR" to "[x86] form reduction intrinsics over raw IR".
spatel added a comment.

Patch updated:
Added a PhaseOrdering test file (vector-reductions-expanded.ll) that checks the output from close to initial IR from clang through -O2 followed by -expand-reductions.

I haven't figured out how to get the new pass manager to mimic that, so for now the file uses the old pass manager only.

That shows the reduction expansion pass creates FP instructions for accumulation that could be avoided, but the backend squashes those. Everything else is identical.

Note the failure to generate fmin/fmax reductions in SLP - it doesn't seem to recognize the min/max IR intrinsics as reduction candidates, but that's an existing/different issue.

We have codegen test coverage for all of the reduction intrinsics too, so that covers everything from intrinsics to x86 asm. So I think we can enable this now without any regressions.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80867/new/

https://reviews.llvm.org/D80867

Files:
  llvm/lib/Target/X86/X86TargetTransformInfo.h
  llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
  llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
  llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
  llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
  llvm/test/Transforms/LoopVectorize/X86/pr42674.ll
  llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
  llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
  llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
  llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
  llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
  llvm/test/Transforms/SLPVectorizer/X86/PR35628_1.ll
  llvm/test/Transforms/SLPVectorizer/X86/PR35628_2.ll
  llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
  llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll
  llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
  llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
  llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
  llvm/test/Transforms/SLPVectorizer/X86/reassociated-loads.ll
  llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
  llvm/test/Transforms/SLPVectorizer/X86/reduction_loads.ll
  llvm/test/Transforms/SLPVectorizer/X86/reduction_unrolled.ll
  llvm/test/Transforms/SLPVectorizer/X86/remark_horcost.ll
  llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
  llvm/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll
  llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll
  llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
  llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll
  llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll

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