[PATCH] D81076: [PowerPC] Custom lower rotl v1i128 to vector_shuffle.

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9622
+  if (Op.getValueType() != MVT::v1i128)
+    return SDValue();
+  SDLoc dl(Op);
----------------
It will have problem if return SDValue() when lower the ROTL. I would change it as assertion.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9634
+                             DAG.getUNDEF(MVT::v16i8), Mask);
+    if (Shuffle)
+      return DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, Shuffle);
----------------
nit: 
if (SDValue Shuffle = xxxx)
  return Shuffle;


================
Comment at: llvm/test/CodeGen/PowerPC/pr45628.ll:142
 ; CHECK-NOVSX:       # %bb.0: # %entry
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI7_0 at toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI7_0 at toc@l
-; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
-; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI7_1 at toc@ha
-; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI7_1 at toc@l
-; CHECK-NOVSX-NEXT:    vslo v4, v2, v3
-; CHECK-NOVSX-NEXT:    vspltb v3, v3, 15
-; CHECK-NOVSX-NEXT:    vsl v3, v4, v3
-; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
-; CHECK-NOVSX-NEXT:    vsro v2, v2, v4
-; CHECK-NOVSX-NEXT:    vspltb v4, v4, 15
-; CHECK-NOVSX-NEXT:    vsr v2, v2, v4
-; CHECK-NOVSX-NEXT:    vor v2, v3, v2
+; CHECK-NOVSX-NEXT:    addi r3, r1, -32
+; CHECK-NOVSX-NEXT:    stvx v2, 0, r3
----------------
lkail wrote:
> New sequence looks getting more memory ops than original one.
I believe they are using to move the VSR to two GPR. And yes, we need to take a more look to see if there is any better way to handle it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81076/new/

https://reviews.llvm.org/D81076