[PATCH] D80999: [ARM][CodeGen] Enabling spilling of high registers in RegAllocFast for Thumb1

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

This is intentionally not addressing greedy regalloc, I guess.

I think ConstantIslands currently assumes LR is never live in Thumb1 mode.  Have you looked at that at all?  (Last time I looked at this, there was also ThumbRegisterInfo::saveScavengerRegister, but that's gone now.)



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Comment at: llvm/lib/CodeGen/RegAllocFast.cpp:346
+    MCPhysReg SpillReg =
+        getFreeRegForAllocation(*Before, *SpillRC, Register(), Register());
+    BuildMI(*MBB, Before, Before->getDebugLoc(), TII->get(TargetOpcode::COPY),
----------------
Is it possible to spuriously run out of registers?  Say you have an inline asm that requires r0-r8.  You allocate r0-r7, then try to allocate r8, then we run out of registers because r0-r7 were already reserved.


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https://reviews.llvm.org/D80999