[PATCH] D80946: [AMDGPU/MemOpsCluster] Code clean-up around accessing of memory operand width

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:277
   OffsetIsScalable = false;
-  const MachineOperand *BaseOp, *OffsetOp, *MOp;
+  const MachineOperand *BaseOp, *OffsetOp, *MO;
 
----------------
MO is not a very descriptive name. How about DataOp (or DataOpIdx when you switch to using getNamedOperandIdx)?


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.h:836
 
+  unsigned getOpSize(const MachineInstr &MI, const MachineOperand &MO,
+                     const MachineRegisterInfo &MRI) const {
----------------
There's no need for this new overload if you use getNamedOperandIdx instead of getNamedOperand and pass the index into getOpSize(MI, OpNo).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80946/new/

https://reviews.llvm.org/D80946