[PATCH] D80999: [ARM][CodeGen] Enabling spilling of high registers in RegAllocFast for Thumb1

[Lucas Prates via Phabricator via llvm-commits]

pratlucas created this revision.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls, qcolombet, MatzeB.
Herald added a project: LLVM.
pratlucas added reviewers: eli.friedman, thopre, qcolombet, abeserminji, MatzeB, arsenm, petpav01.
Herald added a subscriber: wdng.

High registers - r8 until r12 - have no load/store instructions in
Thumb1 and, therefore, are not generally allocatable in Thumb1 mode.
When registers of this class are clobbered by inline assembly, though,
the Fast Register Allocator may be required to spill those registers.

In such conditions, the Fast Register Allocator hit an assertion failure
when trying to spill high registers to the satck through
TargetRegisterInfo's `storeRegToStackSlot`.

This patch enables the register allocator to use an auxiliary register
for the spill operation, introducing a new hook for the target inform
the proper register class to be used in loads/stores.

This patch is based on the discussion from D49364 <https://reviews.llvm.org/D49364>. The changes were written
from scratch, as there were significant changes to RegAllocFast since then.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80999

Files:
  llvm/include/llvm/CodeGen/TargetRegisterInfo.h
  llvm/lib/CodeGen/RegAllocFast.cpp
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
  llvm/test/CodeGen/Thumb/high-reg-spill.mir
  llvm/test/CodeGen/Thumb/no-regs-available.mir

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