[llvm] ec2e9ce - [VE] Support I32/F32 registers in assembler parser
Simon Moll via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 2 01:23:31 PDT 2020
Author: Kazushi (Jam) Marukawa
Date: 2020-06-02T10:22:45+02:00
New Revision: ec2e9ce73e6c2d70523f7e51a23bf07f998ebecd
URL: https://github.com/llvm/llvm-project/commit/ec2e9ce73e6c2d70523f7e51a23bf07f998ebecd
DIFF: https://github.com/llvm/llvm-project/commit/ec2e9ce73e6c2d70523f7e51a23bf07f998ebecd.diff
LOG: [VE] Support I32/F32 registers in assembler parser
Summary:
Support I32/F32 registers in assembler parser and add regression tests of LD/ST
instructions.
Differential Revision: https://reviews.llvm.org/D80777
Added:
llvm/test/MC/VE/LD.s
llvm/test/MC/VE/ST.s
Modified:
llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
index 24147d0cd8c0..30dd581eddb5 100644
--- a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
+++ b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
@@ -62,6 +62,9 @@ class VEAsmParser : public MCTargetAsmParser {
SMLoc NameLoc, OperandVector &Operands) override;
bool ParseDirective(AsmToken DirectiveID) override;
+ unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
+ unsigned Kind) override;
+
// Custom parse functions for VE specific operands.
OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
@@ -78,6 +81,30 @@ class VEAsmParser : public MCTargetAsmParser {
} // end anonymous namespace
+static const MCPhysReg I32Regs[64] = {
+ VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
+ VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
+ VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
+ VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
+ VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
+ VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
+ VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
+ VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
+ VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
+ VE::SW63};
+
+static const MCPhysReg F32Regs[64] = {
+ VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6,
+ VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13,
+ VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20,
+ VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,
+ VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,
+ VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,
+ VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,
+ VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,
+ VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
+ VE::SF63};
+
namespace {
/// VEOperand - Instances of this class represent a parsed VE machine
@@ -329,6 +356,24 @@ class VEOperand : public MCParsedAsmOperand {
return Op;
}
+ static bool MorphToI32Reg(VEOperand &Op) {
+ unsigned Reg = Op.getReg();
+ unsigned regIdx = Reg - VE::SX0;
+ if (regIdx > 63)
+ return false;
+ Op.Reg.RegNum = I32Regs[regIdx];
+ return true;
+ }
+
+ static bool MorphToF32Reg(VEOperand &Op) {
+ unsigned Reg = Op.getReg();
+ unsigned regIdx = Reg - VE::SX0;
+ if (regIdx > 63)
+ return false;
+ Op.Reg.RegNum = F32Regs[regIdx];
+ return true;
+ }
+
static std::unique_ptr<VEOperand>
MorphToMEMrri(unsigned Base, unsigned Index, std::unique_ptr<VEOperand> Op) {
const MCExpr *Imm = Op->getImm();
@@ -690,3 +735,25 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVEAsmParser() {
#define GET_REGISTER_MATCHER
#define GET_MATCHER_IMPLEMENTATION
#include "VEGenAsmMatcher.inc"
+
+unsigned VEAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
+ unsigned Kind) {
+ VEOperand &Op = (VEOperand &)GOp;
+
+ // VE uses identical register name for all registers like both
+ // F32 and I32 uses "%s23". Need to convert the name of them
+ // for validation.
+ switch (Kind) {
+ default:
+ break;
+ case MCK_F32:
+ if (Op.isReg() && VEOperand::MorphToF32Reg(Op))
+ return MCTargetAsmParser::Match_Success;
+ break;
+ case MCK_I32:
+ if (Op.isReg() && VEOperand::MorphToI32Reg(Op))
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ return Match_InvalidOperand;
+}
diff --git a/llvm/test/MC/VE/LD.s b/llvm/test/MC/VE/LD.s
new file mode 100644
index 000000000000..8f18a489db93
--- /dev/null
+++ b/llvm/test/MC/VE/LD.s
@@ -0,0 +1,45 @@
+# RUN: llvm-mc -triple ve-unknown-unknown --show-encoding %s | FileCheck %s
+
+# CHECK: ld %s11, 8199
+# CHECK: encoding: [0x07,0x20,0x00,0x00,0x00,0x00,0x0b,0x01]
+ld %s11, 8199
+
+# CHECK: ld %s11, 20(%s11)
+# CHECK: encoding: [0x14,0x00,0x00,0x00,0x00,0x8b,0x0b,0x01]
+ld %s11, 20(%s11)
+
+# CHECK: ld %s11, -1(, %s11)
+# CHECK: encoding: [0xff,0xff,0xff,0xff,0x8b,0x00,0x0b,0x01]
+ld %s11, -1(, %s11)
+
+# CHECK: ld %s11, 20(%s10, %s11)
+# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x01]
+ld %s11, 20(%s10, %s11)
+
+# CHECK: ldu %s11, 20(%s10, %s11)
+# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x02]
+ldu %s11, 20(%s10, %s11)
+
+# CHECK: ldl.sx %s11, 20(%s10, %s11)
+# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x03]
+ldl.sx %s11, 20(%s10, %s11)
+
+# CHECK: ldl.zx %s11, 20(%s10, %s11)
+# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x8b,0x03]
+ldl.zx %s11, 20(%s10, %s11)
+
+# CHECK: ld2b.sx %s11, 20(%s10, %s11)
+# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x04]
+ld2b.sx %s11, 20(%s10, %s11)
+
+# CHECK: ld2b.zx %s11, 20(%s10, %s11)
+# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x8b,0x04]
+ld2b.zx %s11, 20(%s10, %s11)
+
+# CHECK: ld1b.sx %s11, 20(%s10, %s11)
+# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x05]
+ld1b.sx %s11, 20(%s10, %s11)
+
+# CHECK: ld1b.zx %s11, 20(%s10, %s11)
+# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x8b,0x05]
+ld1b.zx %s11, 20(%s10, %s11)
diff --git a/llvm/test/MC/VE/ST.s b/llvm/test/MC/VE/ST.s
new file mode 100644
index 000000000000..33ac5024868a
--- /dev/null
+++ b/llvm/test/MC/VE/ST.s
@@ -0,0 +1,33 @@
+# RUN: llvm-mc -triple ve-unknown-unknown --show-encoding %s | FileCheck %s
+
+# CHECK: st %s11, 32767
+# CHECK: encoding: [0xff,0x7f,0x00,0x00,0x00,0x00,0x0b,0x11]
+st %s11, 32767
+
+# CHECK: st %s11, 20(%s11)
+# CHECK: encoding: [0x14,0x00,0x00,0x00,0x00,0x8b,0x0b,0x11]
+st %s11, 20(%s11)
+
+# CHECK: st %s11, -1(, %s11)
+# CHECK: encoding: [0xff,0xff,0xff,0xff,0x8b,0x00,0x0b,0x11]
+st %s11, -1(, %s11)
+
+# CHECK: st %s11, 20(%s10, %s11)
+# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x11]
+st %s11, 20(%s10, %s11)
+
+# CHECK: stu %s11, 20(%s10, %s11)
+# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x12]
+stu %s11, 20(%s10, %s11)
+
+# CHECK: stl %s11, 20(%s10, %s11)
+# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x13]
+stl %s11, 20(%s10, %s11)
+
+# CHECK: st2b %s11, 20(%s10, %s11)
+# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x14]
+st2b %s11, 20(%s10, %s11)
+
+# CHECK: st1b %s11, 20(%s10, %s11)
+# CHECK: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x15]
+st1b %s11, 20(%s10, %s11)
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