[PATCH] D80946: [AMDGPU/MemOpsCluster] Code clean-up around accessing of memory operand width

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.h:836
 
+  unsigned getOpSize(const MachineInstr &MI, const MachineOperand &MO) const {
+    const TargetRegisterClass *DstRC = RI.getRegClassForReg(
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Losing the units in the name is a regression. I would also pass in MRI explicitly rather than getting it from the parent function


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  https://reviews.llvm.org/D80946/new/

https://reviews.llvm.org/D80946