[llvm] 1ecf39d - [X86] Fix a place where we created MOVQ2DQ with a DstVT other than v2i64.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-05-30T19:47:07-07:00
New Revision: 1ecf39d607acdb04c2bb5155e5f7265db2484511

URL: https://github.com/llvm/llvm-project/commit/1ecf39d607acdb04c2bb5155e5f7265db2484511
DIFF: https://github.com/llvm/llvm-project/commit/1ecf39d607acdb04c2bb5155e5f7265db2484511.diff

LOG: [X86] Fix a place where we created MOVQ2DQ with a DstVT other than v2i64.

The type profile and isel pattern have this type declared as
being MVT::v2i64. But isel skips the explicit type check due to
the type profile.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 0b114b34186d..6ebd46893f95 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -30002,10 +30002,14 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
     }
 
     if (DstVT.isVector() && SrcVT == MVT::x86mmx) {
+      // FIXME: Use v4f32 for SSE1?
+      assert(Subtarget.hasSSE2() && "Requires SSE2");
       assert(getTypeAction(*DAG.getContext(), DstVT) == TypeWidenVector &&
              "Unexpected type action!");
       EVT WideVT = getTypeToTransformTo(*DAG.getContext(), DstVT);
-      SDValue Res = DAG.getNode(X86ISD::MOVQ2DQ, dl, WideVT, N->getOperand(0));
+      SDValue Res = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64,
+                                N->getOperand(0));
+      Res = DAG.getBitcast(WideVT, Res);
       Results.push_back(Res);
       return;
     }