[PATCH] D80869: [DAG] SimplifyDemandedBits - peek through SHL if we only demand sign bits.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, spatel, efriedma, arsenm.
Herald added subscribers: kerbowa, hiraditya, nhaehnle, wdng, jvesely.
Herald added a project: LLVM.

If we're only demanding the (shifted) sign bits of the shift source value, then we can use the value directly.

This handles SimplifyDemandedBits/SimplifyMultipleUseDemandedBits for both ISD::SHL and X86ISD::VSHLI.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80869

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/sdiv.ll
  llvm/test/CodeGen/X86/bitcast-setcc-128.ll
  llvm/test/CodeGen/X86/funnel-shift.ll
  llvm/test/CodeGen/X86/promote-cmp.ll
  llvm/test/CodeGen/X86/sdiv_fix_sat.ll
  llvm/test/CodeGen/X86/vector-mulfix-legalize.ll
  llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
  llvm/test/CodeGen/X86/vector-reduce-or-bool.ll

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