[PATCH] D80777: [VE] Support I32/F32 registers in assembler parser

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 updated this revision to Diff 267332.
kaz7 retitled this revision from " [VE] Support I32/F32 registers in assembler parser" to "[VE] Support I32/F32 registers in assembler parser".
kaz7 added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80777/new/

https://reviews.llvm.org/D80777

Files:
  llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
  llvm/test/MC/VE/LD.s
  llvm/test/MC/VE/ST.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D80777.267332.patch
Type: text/x-patch
Size: 6532 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200529/2b2eef19/attachment.bin>