[PATCH] D80364: [amdgpu] Teach load widening to handle non-DWORD aligned loads.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

I did some experiments locally and think this can stay in AMDGPUCodeGenPrepare, and doesn't need the split pass. Since you restrict this widening to the case where you're rebasing the load anyway,  I don't think this will cause the same problems with the vectorizer the previous IR load widening had (and may help it even?)

test3 should also come back, but should have the explicit align 4 added to the load. This could also use some loads of i8, and <2 x i8>. We could also extend this to handle wider, sub-dword aligned types but that's a separate patch.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D80364/new/

https://reviews.llvm.org/D80364