[llvm] f6a6de2 - GlobalISel: fix CombinerHelper::matchEqualDefs()

[Stanislav Mekhanoshin via llvm-commits]

Author: Stanislav Mekhanoshin
Date: 2020-05-29T09:30:02-07:00
New Revision: f6a6de288bfb23e45ab2558a9c163132cfe7579a

URL: https://github.com/llvm/llvm-project/commit/f6a6de288bfb23e45ab2558a9c163132cfe7579a
DIFF: https://github.com/llvm/llvm-project/commit/f6a6de288bfb23e45ab2558a9c163132cfe7579a.diff

LOG: GlobalISel: fix CombinerHelper::matchEqualDefs()

This matcher was always returning true for the different
results of a same instruction.

Differential Revision:

Added: 
    llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir

Modified: 
    llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index a3291a6a9712..fbcd4c6f9d9f 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -1549,6 +1549,15 @@ bool CombinerHelper::matchEqualDefs(const MachineOperand &MOP1,
   if (!I2)
     return false;
 
+  // Handle a case like this:
+  //
+  // %0:_(s64), %1:_(s64) = G_UNMERGE_VALUES %2:_(<2 x s64>)
+  //
+  // Even though %0 and %1 are produced by the same instruction they are not
+  // the same values.
+  if (I1 == I2)
+    return MOP1.getReg() == MOP2.getReg();
+
   // If we have an instruction which loads or stores, we can't guarantee that
   // it is identical.
   //

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir
new file mode 100644
index 000000000000..89f58e1e7687
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+
+---
+name:            select_from_
diff erent_results_of_unmerge_values
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; GCN-LABEL: name: select_from_
diff erent_results_of_unmerge_values
+    ; GCN: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
+    ; GCN: [[DEF1:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
+    ; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
+    ; GCN: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[DEF1]](s1), [[UV]], [[UV1]]
+    ; GCN: $vgpr0 = COPY [[SELECT]](s32)
+    ; GCN: SI_RETURN_TO_EPILOG $vgpr0
+    %2:_(<2 x s32>) = G_IMPLICIT_DEF
+    %4:_(s1) = G_IMPLICIT_DEF
+    %0:_(s32), %1:_(s32) = G_UNMERGE_VALUES %2:_(<2 x s32>)
+    %3:_(s32) = G_SELECT %4:_(s1), %0:_, %1:_
+    $vgpr0 = COPY %3
+    SI_RETURN_TO_EPILOG $vgpr0
+
+...
+
+---
+name:            select_from_same_results_of_unmerge_values
+tracksRegLiveness: true
+body:             |
+  bb.0:
+
+    ; GCN-LABEL: name: select_from_same_results_of_unmerge_values
+    ; GCN: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
+    ; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
+    ; GCN: $vgpr0 = COPY [[UV]](s32)
+    ; GCN: SI_RETURN_TO_EPILOG $vgpr0
+    %2:_(<2 x s32>) = G_IMPLICIT_DEF
+    %4:_(s1) = G_IMPLICIT_DEF
+    %0:_(s32), %1:_(s32) = G_UNMERGE_VALUES %2:_(<2 x s32>)
+    %3:_(s32) = G_SELECT %4:_(s1), %0:_, %0:_
+    $vgpr0 = COPY %3
+    SI_RETURN_TO_EPILOG $vgpr0
+
+...