[PATCH] D77152: [SelectionDAG] Better legalization for FSHL and FSHR
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri May 29 08:07:04 PDT 2020
foad marked an inline comment as done.
foad added inline comments.
================
Comment at: llvm/test/CodeGen/X86/vector-fshl-rot-128.ll:1670-1675
; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrlq $50, %xmm1
+; X32-SSE-NEXT: movsd {{.*#+}} xmm1 = xmm1[0,1]
; X32-SSE-NEXT: psllq $14, %xmm0
-; X32-SSE-NEXT: por %xmm1, %xmm0
+; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm0[0,1]
+; X32-SSE-NEXT: orpd %xmm1, %xmm0
----------------
Can anyone suggest what might have caused this regression? We get two presumably redundant movsd instructions:
```
psrlq $50, %xmm1
movsd %xmm1, %xmm1 # xmm1 = xmm1[0,1]
psllq $14, %xmm0
movsd %xmm0, %xmm0 # xmm0 = xmm0[0,1]
orpd %xmm1, %xmm0
```
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D77152/new/
https://reviews.llvm.org/D77152
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