[PATCH] D80616: [CodeGen] Fix warnings in getZeroExtendInReg
David Sherwood via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri May 29 04:18:47 PDT 2020
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4265f1d23cc9: [CodeGen] Fix warnings in getZeroExtendInReg (authored by david-arm).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80616/new/
https://reviews.llvm.org/D80616
Files:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1175,7 +1175,7 @@
"getZeroExtendInReg type should be vector iff the operand "
"type is vector!");
assert((!VT.isVector() ||
- VT.getVectorNumElements() == OpVT.getVectorNumElements()) &&
+ VT.getVectorElementCount() == OpVT.getVectorElementCount()) &&
"Vector element counts must match in getZeroExtendInReg");
assert(VT.bitsLE(OpVT) && "Not extending!");
if (OpVT == VT)
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