[llvm] 4265f1d - [CodeGen] Fix warnings in getZeroExtendInReg

[David Sherwood via llvm-commits]

Author: David Sherwood
Date: 2020-05-29T11:51:07+01:00
New Revision: 4265f1d23cc9d10b9544bafc7a285ca5f143faea

URL: https://github.com/llvm/llvm-project/commit/4265f1d23cc9d10b9544bafc7a285ca5f143faea
DIFF: https://github.com/llvm/llvm-project/commit/4265f1d23cc9d10b9544bafc7a285ca5f143faea.diff

LOG: [CodeGen] Fix warnings in getZeroExtendInReg

We should be using getVectorElementCount() to assert that two types
have the same numbers of elements. I encountered the warnings while
compiling this test:

  CodeGen/AArch64/sve-intrinsics-ld1.ll

Differential Revision: https://reviews.llvm.org/D80616

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 2f277eee8495..bd1a5a4a876e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1175,7 +1175,7 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
          "getZeroExtendInReg type should be vector iff the operand "
          "type is vector!");
   assert((!VT.isVector() ||
-          VT.getVectorNumElements() == OpVT.getVectorNumElements()) &&
+          VT.getVectorElementCount() == OpVT.getVectorElementCount()) &&
          "Vector element counts must match in getZeroExtendInReg");
   assert(VT.bitsLE(OpVT) && "Not extending!");
   if (OpVT == VT)