[PATCH] D77152: [SelectionDAG] Better legalization for FSHL and FSHR

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added a comment.

In D77152#2057762 <https://reviews.llvm.org/D77152#2057762>, @RKSimon wrote:

> IIRC powerpc scalar shift ops can use shift amounts upto the bitwidth (not bitwidth-1) so there might be custom funnel shifts that they can do with that - @hfinkel @nemanjai any thoughts?


The reg+reg shifts consider enough bits of the register that contains the shift amount to shift by `bitwidth * 2 - 1` bits. For example `(i64:x << y) == 0 for 64 <= y < 128`. The immediate forms do not have this property (i.e. there is no way to encode `(i64:x << 64)` since the immediate field is 6 bits.
But even for the reg+reg versions, I can't think of how we can utilize this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77152/new/

https://reviews.llvm.org/D77152