[PATCH] D80741: [llvm][SVE] Reg + reg addressing mode for LD1RO.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli created this revision.
fpetrogalli added reviewers: efriedma, sdesmalen.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, tschuett.
Herald added a project: LLVM.
fpetrogalli added a parent revision: D80738: [llvm][SVE] IR intrinsic for LD1RO..

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80741

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro-addressing-mode-reg-reg.ll

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