[PATCH] D80738: [llvm][SVE] IR intrinsic for LD1RO.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli created this revision.
fpetrogalli added reviewers: sdesmalen, efriedma.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, tschuett.
Herald added a project: LLVM.
fpetrogalli marked an inline comment as done.
fpetrogalli added inline comments.
fpetrogalli added a child revision: D80740: [SveEmitter] Add SVE ACLE for svld1ro..
fpetrogalli added a child revision: D80741: [llvm][SVE] Reg + reg addressing mode for LD1RO..


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11898
 
+static SDValue performLD1ROCombine(SDNode *N, SelectionDAG &DAG) {
+  SDLoc DL(N);
----------------
Note: I am tempted to merge `performLD1ROCombine` and `performLD1RQCombine` in a single function, as they only differ in the ISD node being used to replace the intrinsic. Let me know if this makes sense, I'll update the patch.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11898
 
+static SDValue performLD1ROCombine(SDNode *N, SelectionDAG &DAG) {
+  SDLoc DL(N);
----------------
fpetrogalli wrote:
> Note: I am tempted to merge `performLD1ROCombine` and `performLD1RQCombine` in a single function, as they only differ in the ISD node being used to replace the intrinsic. Let me know if this makes sense, I'll update the patch.
Yes, that makes sense.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80738

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro.ll

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