[PATCH] D80422: Enable `align <n>` to be used in intrinsic definitions.
    Michael Liao via Phabricator via llvm-commits 
    llvm-commits at lists.llvm.org
       
    Wed May 27 09:11:39 PDT 2020
    
    
  
hliao updated this revision to Diff 266559.
hliao added a comment.
remove <tuple> header.
Repository:
  rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80422/new/
https://reviews.llvm.org/D80422
Files:
  llvm/include/llvm/IR/Attributes.h
  llvm/include/llvm/IR/Intrinsics.td
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/include/llvm/IR/IntrinsicsAMDGPU.td
  llvm/include/llvm/IR/IntrinsicsARM.td
  llvm/include/llvm/IR/IntrinsicsBPF.td
  llvm/include/llvm/IR/IntrinsicsHexagon.td
  llvm/include/llvm/IR/IntrinsicsHexagonDep.td
  llvm/include/llvm/IR/IntrinsicsMips.td
  llvm/include/llvm/IR/IntrinsicsNVVM.td
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/include/llvm/IR/IntrinsicsSystemZ.td
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/IR/IntrinsicsXCore.td
  llvm/lib/IR/Attributes.cpp
  llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll
  llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td
  llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td
  llvm/test/TableGen/immarg.td
  llvm/utils/TableGen/CodeGenIntrinsics.h
  llvm/utils/TableGen/CodeGenTarget.cpp
  llvm/utils/TableGen/IntrinsicEmitter.cpp
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