[PATCH] D78772: [AMDGPU] Adapt GCNRegBankReassign for 16 bit subregs

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.h:287-288
   unsigned getChannelFromSubReg(unsigned SubReg) const {
-    return SubReg ? divideCeil(getSubRegIdxOffset(SubReg), 32) : 0;
+    if (!SubReg)
+      return 0;
+    unsigned Offset = getSubRegIdxOffset(SubReg) & ~31u;
----------------
rampitec wrote:
> arsenm wrote:
> > I would expect this to be an assert, but. guess it already handled this case
> That's because hi16 returns 16 as an offset, and then divideCell returns 1 which is plain wrong.
divideCeil(16, 32) returns 1 which is plain right!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78772/new/

https://reviews.llvm.org/D78772