[llvm] 45251ef - [AMDGPU][MC] Corrected v_writelane_b32 to fix a decoding bug

[Dmitry Preobrazhensky via llvm-commits]

Author: Dmitry Preobrazhensky
Date: 2020-05-28T14:43:49+03:00
New Revision: 45251ef5345b3c81c8f394d42d252de039c72566

URL: https://github.com/llvm/llvm-project/commit/45251ef5345b3c81c8f394d42d252de039c72566
DIFF: https://github.com/llvm/llvm-project/commit/45251ef5345b3c81c8f394d42d252de039c72566.diff

LOG: [AMDGPU][MC] Corrected v_writelane_b32 to fix a decoding bug

Corrected vdst_in to match vdst operand type.
See bug 45193: https://bugs.llvm.org/show_bug.cgi?id=45193

Reviewers: arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D80636

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/VOP2Instructions.td
    llvm/lib/Target/AMDGPU/VOP3Instructions.td
    llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 4927c6c2f3f2..86dc179f9421 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -1262,9 +1262,9 @@ defm V_SUBBREV_U32        : VOP2be_Real_gfx6_gfx7<0x02a>;
 
 defm V_READLANE_B32 : VOP2Only_Real_gfx6_gfx7<0x001>;
 
-let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) in {
+let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
   defm V_WRITELANE_B32 : VOP2Only_Real_gfx6_gfx7<0x002>;
-} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in)
+} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
 
 let SubtargetPredicate = isGFX6GFX7 in {
   defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx6_gfx7>;

diff  --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 7e1ac7509719..66a4e62a3be4 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -839,9 +839,9 @@ let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
 
 defm V_READLANE_B32  : VOP3_Real_gfx10<0x360>;
 
-let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) in {
+let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
   defm V_WRITELANE_B32 : VOP3_Real_gfx10<0x361>;
-} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in)
+} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
 
 defm V_XOR3_B32           : VOP3_Real_gfx10<0x178>;
 defm V_LSHLREV_B64        : VOP3_Real_gfx10<0x2ff>;

diff  --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
index 21344f344fa9..89cbaa7f0299 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
@@ -98025,8 +98025,8 @@
 # GFX10: v_trunc_f64_e64 v[5:6], |v[1:2]| ; encoding: [0x05,0x01,0x97,0xd5,0x01,0x01,0x00,0x00]
 0x05,0x01,0x97,0xd5,0x01,0x01,0x00,0x00
 
-# GFX10-FIXME: v_writelane_b32 v255, 0, s2     ; encoding: [0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00]
-# 0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00
+# GFX10: v_writelane_b32 v255, 0, s2     ; encoding: [0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00]
+0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00
 
 # GFX10: v_writelane_b32 v5, -1, s2      ; encoding: [0x05,0x00,0x61,0xd7,0xc1,0x04,0x00,0x00]
 0x05,0x00,0x61,0xd7,0xc1,0x04,0x00,0x00