[PATCH] D80683: [SelectionDAG] Fix up SimplifyDemandedBits for ppcf128

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai created this revision.
nemanjai added reviewers: hfinkel, Carrot, RKSimon, PowerPC.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.
echristo accepted this revision.
echristo added a comment.
This revision is now accepted and ready to land.

Oof. That's painful, but I guess works for now.


On little endian PPC, the order of the doubles in a PPC double-double are reversed. When performing a "demanded bits" simplification, the demanded bits have to be rotated so that the bits come from the correct double.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=45475


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80683

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/PowerPC/pr45475.ll


Index: llvm/test/CodeGen/PowerPC/pr45475.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/pr45475.ll
@@ -0,0 +1,41 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:     -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:     -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:     --check-prefix=CHECK-BE
+define zeroext i1 @ppc128hi(ppc_fp128 %fp) {
+; CHECK-LABEL: ppc128hi:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mffprd r3, f2
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+;
+; CHECK-BE-LABEL: ppc128hi:
+; CHECK-BE:       # %bb.0:
+; CHECK-BE-NEXT:    mffprd r3, f1
+; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    blr
+  %v128 = bitcast ppc_fp128 %fp to i128
+  %shift = lshr i128 %v128, 64
+  %high = trunc i128 %shift to i64
+  %c = icmp slt i64 %high, 0
+  ret i1 %c
+}
+define zeroext i1 @ppc128lo(ppc_fp128 %fp) {
+; CHECK-LABEL: ppc128lo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mffprd r3, f1
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
+;
+; CHECK-BE-LABEL: ppc128lo:
+; CHECK-BE:       # %bb.0:
+; CHECK-BE-NEXT:    mffprd r3, f2
+; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    blr
+  %v128 = bitcast ppc_fp128 %fp to i128
+  %low = trunc i128 %v128 to i64
+  %c = icmp slt i64 %low, 0
+  ret i1 %c
+}
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -846,6 +846,11 @@
 
   // Other users may use these bits.
   EVT VT = Op.getValueType();
+
+  // On little endian, the order of ppcf128 is backwards.
+  if (VT == MVT::ppcf128 && TLO.DAG.getDataLayout().isLittleEndian())
+    DemandedBits = DemandedBits.rotl(64);
+
   if (!Op.getNode()->hasOneUse() && !AssumeSingleUse) {
     if (Depth != 0) {
       // If not at the root, Just compute the Known bits to


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