[PATCH] D80678: [ModuloSchedule] Allow illegal phis to be moved across stages.

[Hendrik Greving via Phabricator via llvm-commits]

hgreving created this revision.
hgreving added a reviewer: ThomasRaoux.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.
hgreving retitled this revision from "ModuloSchedule] Allow illegal phis to be moved across stages." to "[ModuloSchedule] Allow illegal phis to be moved across stages.".

Fixes a trivial but impactful bug where we did not move illegal phis across stages. This
led to incorrect mappings in certain cases.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80678

Files:
  llvm/lib/CodeGen/ModuloSchedule.cpp


Index: llvm/lib/CodeGen/ModuloSchedule.cpp
===================================================================
--- llvm/lib/CodeGen/ModuloSchedule.cpp
+++ llvm/lib/CodeGen/ModuloSchedule.cpp
@@ -1629,18 +1629,21 @@
     MachineInstr *MI = &*I++;
     if (MI->isPHI()) {
       // This is an illegal PHI. If we move any instructions using an illegal
-      // PHI, we need to create a legal Phi
-      Register PhiR = MI->getOperand(0).getReg();
-      auto RC = MRI.getRegClass(PhiR);
-      Register NR = MRI.createVirtualRegister(RC);
-      MachineInstr *NI = BuildMI(*DestBB, DestBB->getFirstNonPHI(), DebugLoc(),
-                                 TII->get(TargetOpcode::PHI), NR)
-                             .addReg(PhiR)
-                             .addMBB(SourceBB);
-      BlockMIs[{DestBB, CanonicalMIs[MI]}] = NI;
-      CanonicalMIs[NI] = CanonicalMIs[MI];
-      Remaps[PhiR] = NR;
-      continue;
+      // PHI, we need to create a legal Phi.
+      if (getStage(MI) != Stage) {
+        // The legal Phi is not necessary if the illegal phi's stage
+        // is being moved.
+        Register PhiR = MI->getOperand(0).getReg();
+        auto RC = MRI.getRegClass(PhiR);
+        Register NR = MRI.createVirtualRegister(RC);
+        MachineInstr *NI = BuildMI(*DestBB, DestBB->getFirstNonPHI(),
+                                   DebugLoc(), TII->get(TargetOpcode::PHI), NR)
+                               .addReg(PhiR)
+                               .addMBB(SourceBB);
+        BlockMIs[{DestBB, CanonicalMIs[MI]}] = NI;
+        CanonicalMIs[NI] = CanonicalMIs[MI];
+        Remaps[PhiR] = NR;
+      }
     }
     if (getStage(MI) != Stage)
       continue;


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