[PATCH] D80625: AMDGPU: Fix dropping MI flags when rewriting instructions

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 27 06:27:50 PDT 2020


arsenm created this revision.
arsenm added reviewers: rampitec, kerbowa, vpykhtin.
Herald added subscribers: kbarton, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, nemanjai, kzhuravl.
Herald added a project: LLVM.

All 3 passes that change instruction encodings were dropping MI
flags. This avoids scheduling regressions caused by setting
mayRaiseFPExceptions on FP instructions for non-strictfp functions.


https://reviews.llvm.org/D80625

Files:
  llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
  llvm/test/CodeGen/AMDGPU/dpp_combine.mir
  llvm/test/CodeGen/AMDGPU/sdwa-ops.mir
  llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
  llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir

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