[PATCH] D80524: [ARM] Extra MVE VMLAV reduction patterns

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> There are some tests that end up looking worse, but are quite artificial due to passing half vector types through a call boundary. I would not expect the vmull to realistically come up like that, and a vmlava is likely better a lot of the time.

Looking at the tests, I think the key distinction in the cases that get "worse" is that sign/zero-extend can be folded into the multiply.  It's not really related to the calling convention.  That said, not sure how likely that is to come up in practice... I guess if it's produced by a load, we can sign/zero-extend for free?


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https://reviews.llvm.org/D80524