[llvm] fa038e0 - [x86] favor vector constant load to avoid GPR to XMM transfer, part 2
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Mon May 25 05:07:14 PDT 2020
Author: Sanjay Patel
Date: 2020-05-25T08:01:48-04:00
New Revision: fa038e03504c7d0dfd438b1dfdd6da7081e75617
URL: https://github.com/llvm/llvm-project/commit/fa038e03504c7d0dfd438b1dfdd6da7081e75617
DIFF: https://github.com/llvm/llvm-project/commit/fa038e03504c7d0dfd438b1dfdd6da7081e75617.diff
LOG: [x86] favor vector constant load to avoid GPR to XMM transfer, part 2
This replaces the build_vector lowering code that was just added in
D80013
and matches the pattern later from the x86-specific "vzext_movl".
That seems to result in the same or better improvements and gets rid
of the 'TODO' items from that patch.
AFAICT, we always shrink wider constant vectors to 128-bit on these
patterns, so we still get the implicit zero-extension to ymm/zmm
without wasting space on larger vector constants. There's a trade-off
there because that means we miss potential load-folding.
Similarly, we could load scalar constants here with implicit
zero-extension even to 128-bit. That saves constant space, but it
means we forego load-folding, and so it increases register pressure.
This seems like a good middle-ground between those 2 options.
Differential Revision: https://reviews.llvm.org/D80131
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/avx-load-store.ll
llvm/test/CodeGen/X86/avx2-arith.ll
llvm/test/CodeGen/X86/combine-udiv.ll
llvm/test/CodeGen/X86/fcmp-constant.ll
llvm/test/CodeGen/X86/insert-into-constant-vector.ll
llvm/test/CodeGen/X86/packss.ll
llvm/test/CodeGen/X86/pshufb-mask-comments.ll
llvm/test/CodeGen/X86/ret-mmx.ll
llvm/test/CodeGen/X86/sad.ll
llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
llvm/test/CodeGen/X86/vec_set-A.ll
llvm/test/CodeGen/X86/vec_shift2.ll
llvm/test/CodeGen/X86/vector-lzcnt-128.ll
llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
llvm/test/CodeGen/X86/vector-shuffle-v1.ll
llvm/test/CodeGen/X86/vector-tzcnt-128.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 5fc8448d1e72..eab9f14bec91 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -10209,15 +10209,6 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
if (NumZero == 0)
return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
- // Just load a vector integer constant. Loading is better for code size,
- // avoids move GPR immediate --> XMM, and reduces register pressure.
- if (IsAllConstants && VT.isInteger()) {
- // TODO: Remove -1 restriction with demanded elements improvement?
- // TODO: Insert 128-bit load into wider undef vector?
- if (VT.is128BitVector() && !isAllOnesConstant(Item))
- return SDValue();
- }
-
if (EltVT == MVT::i32 || EltVT == MVT::f32 || EltVT == MVT::f64 ||
(EltVT == MVT::i64 && Subtarget.is64Bit())) {
assert((VT.is128BitVector() || VT.is256BitVector() ||
@@ -35858,6 +35849,30 @@ static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG,
}
}
+ // Load a scalar integer constant directly to XMM instead of transferring an
+ // immediate value from GPR.
+ // vzext_movl (scalar_to_vector C) --> load [C,0...]
+ if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
+ if (auto *C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
+ // Create a vector constant - scalar constant followed by zeros.
+ EVT ScalarVT = N0.getOperand(0).getValueType();
+ Type *ScalarTy = ScalarVT.getTypeForEVT(*DAG.getContext());
+ unsigned NumElts = VT.getVectorNumElements();
+ Constant *Zero = ConstantInt::getNullValue(ScalarTy);
+ SmallVector<Constant *, 32> ConstantVec(NumElts, Zero);
+ ConstantVec[0] = const_cast<ConstantInt *>(C->getConstantIntValue());
+
+ // Load the vector constant from constant pool.
+ MVT PVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
+ SDValue CP = DAG.getConstantPool(ConstantVector::get(ConstantVec), PVT);
+ MachinePointerInfo MPI =
+ MachinePointerInfo::getConstantPool(DAG.getMachineFunction());
+ Align Alignment = cast<ConstantPoolSDNode>(CP)->getAlign();
+ return DAG.getLoad(VT, DL, DAG.getEntryNode(), CP, MPI, Alignment,
+ MachineMemOperand::MOLoad);
+ }
+ }
+
return SDValue();
}
case X86ISD::BLENDI: {
diff --git a/llvm/test/CodeGen/X86/avx-load-store.ll b/llvm/test/CodeGen/X86/avx-load-store.ll
index 1b3c35855ae9..718449d7a771 100644
--- a/llvm/test/CodeGen/X86/avx-load-store.ll
+++ b/llvm/test/CodeGen/X86/avx-load-store.ll
@@ -220,8 +220,7 @@ define void @f_f() nounwind {
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB9_4
; CHECK-NEXT: # %bb.3: # %cif_mixed_test_all
-; CHECK-NEXT: movl $-1, %eax
-; CHECK-NEXT: vmovd %eax, %xmm0
+; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,0,0,0]
; CHECK-NEXT: vmaskmovps %ymm0, %ymm0, (%rax)
; CHECK-NEXT: .LBB9_4: # %cif_mixed_test_any_check
;
@@ -238,13 +237,12 @@ define void @f_f() nounwind {
; CHECK_O0-NEXT: jne .LBB9_3
; CHECK_O0-NEXT: jmp .LBB9_4
; CHECK_O0-NEXT: .LBB9_3: # %cif_mixed_test_all
-; CHECK_O0-NEXT: movl $-1, %eax
-; CHECK_O0-NEXT: vmovd %eax, %xmm0
+; CHECK_O0-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967295,0,0,0]
; CHECK_O0-NEXT: vmovdqa %xmm0, %xmm0
; CHECK_O0-NEXT: vmovaps %xmm0, %xmm1
-; CHECK_O0-NEXT: # implicit-def: $rcx
+; CHECK_O0-NEXT: # implicit-def: $rax
; CHECK_O0-NEXT: # implicit-def: $ymm2
-; CHECK_O0-NEXT: vmaskmovps %ymm2, %ymm1, (%rcx)
+; CHECK_O0-NEXT: vmaskmovps %ymm2, %ymm1, (%rax)
; CHECK_O0-NEXT: .LBB9_4: # %cif_mixed_test_any_check
allocas:
br i1 undef, label %cif_mask_all, label %cif_mask_mixed
diff --git a/llvm/test/CodeGen/X86/avx2-arith.ll b/llvm/test/CodeGen/X86/avx2-arith.ll
index 39a81a2dc020..b694b98d04c4 100644
--- a/llvm/test/CodeGen/X86/avx2-arith.ll
+++ b/llvm/test/CodeGen/X86/avx2-arith.ll
@@ -347,15 +347,13 @@ define <8 x i16> @mul_const8(<8 x i16> %x) {
define <8 x i32> @mul_const9(<8 x i32> %x) {
; X32-LABEL: mul_const9:
; X32: # %bb.0:
-; X32-NEXT: movl $2, %eax
-; X32-NEXT: vmovd %eax, %xmm1
+; X32-NEXT: vmovdqa {{.*#+}} xmm1 = [2,0,0,0]
; X32-NEXT: vpmulld %ymm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: mul_const9:
; X64: # %bb.0:
-; X64-NEXT: movl $2, %eax
-; X64-NEXT: vmovd %eax, %xmm1
+; X64-NEXT: vmovdqa {{.*#+}} xmm1 = [2,0,0,0]
; X64-NEXT: vpmulld %ymm1, %ymm0, %ymm0
; X64-NEXT: retq
%y = mul <8 x i32> %x, <i32 2, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
diff --git a/llvm/test/CodeGen/X86/combine-udiv.ll b/llvm/test/CodeGen/X86/combine-udiv.ll
index c06719b91e27..e6d7aac92616 100644
--- a/llvm/test/CodeGen/X86/combine-udiv.ll
+++ b/llvm/test/CodeGen/X86/combine-udiv.ll
@@ -590,9 +590,7 @@ define <8 x i16> @combine_vec_udiv_nonuniform2(<8 x i16> %x) {
;
; XOP-LABEL: combine_vec_udiv_nonuniform2:
; XOP: # %bb.0:
-; XOP-NEXT: movl $65535, %eax # imm = 0xFFFF
-; XOP-NEXT: vmovd %eax, %xmm1
-; XOP-NEXT: vpshlw %xmm1, %xmm0, %xmm0
+; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq
@@ -664,31 +662,17 @@ define <16 x i8> @combine_vec_udiv_nonuniform4(<16 x i8> %x) {
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: retq
;
-; AVX1-LABEL: combine_vec_udiv_nonuniform4:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
-; AVX1-NEXT: vpackuswb %xmm1, %xmm1, %xmm1
-; AVX1-NEXT: vpsrlw $7, %xmm1, %xmm1
-; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX1-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: combine_vec_udiv_nonuniform4:
-; AVX2: # %bb.0:
-; AVX2-NEXT: movl $171, %eax
-; AVX2-NEXT: vmovd %eax, %xmm1
-; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX2-NEXT: vpmullw %xmm1, %xmm2, %xmm1
-; AVX2-NEXT: vpsrlw $8, %xmm1, %xmm1
-; AVX2-NEXT: vpackuswb %xmm1, %xmm1, %xmm1
-; AVX2-NEXT: vpsrlw $7, %xmm1, %xmm1
-; AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
-; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
-; AVX2-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
-; AVX2-NEXT: retq
+; AVX-LABEL: combine_vec_udiv_nonuniform4:
+; AVX: # %bb.0:
+; AVX-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vpsrlw $8, %xmm1, %xmm1
+; AVX-NEXT: vpackuswb %xmm1, %xmm1, %xmm1
+; AVX-NEXT: vpsrlw $7, %xmm1, %xmm1
+; AVX-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
+; AVX-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
+; AVX-NEXT: retq
;
; XOP-LABEL: combine_vec_udiv_nonuniform4:
; XOP: # %bb.0:
diff --git a/llvm/test/CodeGen/X86/fcmp-constant.ll b/llvm/test/CodeGen/X86/fcmp-constant.ll
index 239830f98089..481a32b39dd3 100644
--- a/llvm/test/CodeGen/X86/fcmp-constant.ll
+++ b/llvm/test/CodeGen/X86/fcmp-constant.ll
@@ -92,8 +92,7 @@ define <2 x i64> @fcmp_ueq_v2f64_undef() {
define <2 x i64> @fcmp_ueq_v2f64_undef_elt() {
; CHECK-LABEL: fcmp_ueq_v2f64_undef_elt:
; CHECK: # %bb.0:
-; CHECK-NEXT: movq $-1, %rax
-; CHECK-NEXT: movq %rax, %xmm0
+; CHECK-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551615,0]
; CHECK-NEXT: retq
%1 = fcmp ueq <2 x double> <double 0x3FF0000000000000, double 0xFFEFFFFFFFFFFFFF>, <double undef, double 0x3FF0000000000000>
%2 = sext <2 x i1> %1 to <2 x i64>
diff --git a/llvm/test/CodeGen/X86/insert-into-constant-vector.ll b/llvm/test/CodeGen/X86/insert-into-constant-vector.ll
index 18d57e928055..779c91ab2575 100644
--- a/llvm/test/CodeGen/X86/insert-into-constant-vector.ll
+++ b/llvm/test/CodeGen/X86/insert-into-constant-vector.ll
@@ -129,10 +129,8 @@ define <4 x i32> @elt3_v4i32(i32 %x) {
define <2 x i64> @elt0_v2i64(i64 %x) {
; X32SSE-LABEL: elt0_v2i64:
; X32SSE: # %bb.0:
-; X32SSE-NEXT: movl $1, %eax
-; X32SSE-NEXT: movd %eax, %xmm1
-; X32SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
-; X32SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X32SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
+; X32SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],mem[0]
; X32SSE-NEXT: retl
;
; X64SSE2-LABEL: elt0_v2i64:
@@ -150,10 +148,8 @@ define <2 x i64> @elt0_v2i64(i64 %x) {
;
; X32AVX-LABEL: elt0_v2i64:
; X32AVX: # %bb.0:
-; X32AVX-NEXT: movl $1, %eax
-; X32AVX-NEXT: vmovd %eax, %xmm0
-; X32AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
-; X32AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; X32AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X32AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],mem[0]
; X32AVX-NEXT: retl
;
; X64AVX-LABEL: elt0_v2i64:
@@ -365,10 +361,9 @@ define <8 x float> @elt6_v8f32(float %x) {
define <8 x i64> @elt5_v8i64(i64 %x) {
; X32SSE-LABEL: elt5_v8i64:
; X32SSE: # %bb.0:
-; X32SSE-NEXT: movl $4, %eax
-; X32SSE-NEXT: movd %eax, %xmm2
-; X32SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
-; X32SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; X32SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
+; X32SSE-NEXT: movaps {{.*#+}} xmm2 = [4,0,0,0]
+; X32SSE-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; X32SSE-NEXT: movaps {{.*#+}} xmm0 = [42,0,1,0]
; X32SSE-NEXT: movaps {{.*#+}} xmm1 = [2,0,3,0]
; X32SSE-NEXT: movaps {{.*#+}} xmm3 = [6,0,7,0]
@@ -395,10 +390,9 @@ define <8 x i64> @elt5_v8i64(i64 %x) {
;
; X32AVX1-LABEL: elt5_v8i64:
; X32AVX1: # %bb.0:
-; X32AVX1-NEXT: movl $4, %eax
-; X32AVX1-NEXT: vmovd %eax, %xmm0
-; X32AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
-; X32AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X32AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X32AVX1-NEXT: vmovaps {{.*#+}} xmm1 = [4,0,0,0]
+; X32AVX1-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; X32AVX1-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm0, %ymm1
; X32AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0]
; X32AVX1-NEXT: retl
@@ -413,11 +407,10 @@ define <8 x i64> @elt5_v8i64(i64 %x) {
;
; X32AVX2-LABEL: elt5_v8i64:
; X32AVX2: # %bb.0:
-; X32AVX2-NEXT: movl $4, %eax
-; X32AVX2-NEXT: vmovd %eax, %xmm0
-; X32AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
-; X32AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; X32AVX2-NEXT: vinserti128 $1, {{\.LCPI.*}}, %ymm0, %ymm1
+; X32AVX2-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; X32AVX2-NEXT: vmovaps {{.*#+}} xmm1 = [4,0,0,0]
+; X32AVX2-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0]
+; X32AVX2-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm0, %ymm1
; X32AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0]
; X32AVX2-NEXT: retl
;
@@ -431,13 +424,12 @@ define <8 x i64> @elt5_v8i64(i64 %x) {
;
; X32AVX512F-LABEL: elt5_v8i64:
; X32AVX512F: # %bb.0:
-; X32AVX512F-NEXT: vmovdqa {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0]
-; X32AVX512F-NEXT: movl $4, %eax
-; X32AVX512F-NEXT: vmovd %eax, %xmm1
-; X32AVX512F-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
-; X32AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; X32AVX512F-NEXT: vinserti128 $1, {{\.LCPI.*}}, %ymm1, %ymm1
-; X32AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; X32AVX512F-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0]
+; X32AVX512F-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
+; X32AVX512F-NEXT: vmovaps {{.*#+}} xmm2 = [4,0,0,0]
+; X32AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
+; X32AVX512F-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm1, %ymm1
+; X32AVX512F-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; X32AVX512F-NEXT: retl
;
; X64AVX512F-LABEL: elt5_v8i64:
diff --git a/llvm/test/CodeGen/X86/packss.ll b/llvm/test/CodeGen/X86/packss.ll
index 9c8d1f301f62..9a4025ab75e4 100644
--- a/llvm/test/CodeGen/X86/packss.ll
+++ b/llvm/test/CodeGen/X86/packss.ll
@@ -159,13 +159,12 @@ define <8 x i16> @trunc_ashr_v4i64_demandedelts(<4 x i64> %a0) {
; X86-SSE-NEXT: psllq $63, %xmm1
; X86-SSE-NEXT: psllq $63, %xmm0
; X86-SSE-NEXT: psrlq $63, %xmm0
-; X86-SSE-NEXT: movdqa {{.*#+}} xmm2 = <1,0,u,u>
+; X86-SSE-NEXT: movdqa {{.*#+}} xmm2 = [1,0,0,0]
; X86-SSE-NEXT: pxor %xmm2, %xmm0
-; X86-SSE-NEXT: pcmpeqd %xmm3, %xmm3
-; X86-SSE-NEXT: paddq %xmm3, %xmm0
+; X86-SSE-NEXT: psubq %xmm2, %xmm0
; X86-SSE-NEXT: psrlq $63, %xmm1
; X86-SSE-NEXT: pxor %xmm2, %xmm1
-; X86-SSE-NEXT: paddq %xmm3, %xmm1
+; X86-SSE-NEXT: psubq %xmm2, %xmm1
; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; X86-SSE-NEXT: packssdw %xmm1, %xmm0
diff --git a/llvm/test/CodeGen/X86/pshufb-mask-comments.ll b/llvm/test/CodeGen/X86/pshufb-mask-comments.ll
index 9a1a000db93c..416b5c8cb096 100644
--- a/llvm/test/CodeGen/X86/pshufb-mask-comments.ll
+++ b/llvm/test/CodeGen/X86/pshufb-mask-comments.ll
@@ -54,7 +54,7 @@ define <16 x i8> @test4(<16 x i8> %V, <2 x i64>* %P) {
define <16 x i8> @test5(<16 x i8> %V) {
; CHECK-LABEL: test5:
; CHECK: # %bb.0:
-; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1,0]
+; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1,0,0,0]
; CHECK-NEXT: movaps %xmm1, (%rax)
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1,1]
; CHECK-NEXT: movaps %xmm1, (%rax)
diff --git a/llvm/test/CodeGen/X86/ret-mmx.ll b/llvm/test/CodeGen/X86/ret-mmx.ll
index bca47e182953..8c2ded4ebb36 100644
--- a/llvm/test/CodeGen/X86/ret-mmx.ll
+++ b/llvm/test/CodeGen/X86/ret-mmx.ll
@@ -32,7 +32,7 @@ define <1 x i64> @t2() nounwind {
define <2 x i32> @t3() nounwind {
; CHECK-LABEL: t3:
; CHECK: ## %bb.0:
-; CHECK-NEXT: movaps {{.*#+}} xmm0 = <1,0,u,u>
+; CHECK-NEXT: movaps {{.*#+}} xmm0 = [1,0,0,0]
; CHECK-NEXT: retq
ret <2 x i32> <i32 1, i32 0>
}
diff --git a/llvm/test/CodeGen/X86/sad.ll b/llvm/test/CodeGen/X86/sad.ll
index 66a8661698a5..006dd3d5ff17 100644
--- a/llvm/test/CodeGen/X86/sad.ll
+++ b/llvm/test/CodeGen/X86/sad.ll
@@ -544,8 +544,7 @@ define i32 @sad_2i8() nounwind {
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: movq $-1024, %rax # imm = 0xFC00
-; SSE2-NEXT: movl $65535, %ecx # imm = 0xFFFF
-; SSE2-NEXT: movd %ecx, %xmm1
+; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,0,0]
; SSE2-NEXT: .p2align 4, 0x90
; SSE2-NEXT: .LBB3_1: # %vector.body
; SSE2-NEXT: # =>This Inner Loop Header: Depth=1
@@ -995,54 +994,20 @@ define i32 @sad_unroll_nonzero_initial(<16 x i8>* %arg, <16 x i8>* %arg1, <16 x
; SSE2-NEXT: movd %xmm1, %eax
; SSE2-NEXT: retq
;
-; AVX1-LABEL: sad_unroll_nonzero_initial:
-; AVX1: # %bb.0: # %bb
-; AVX1-NEXT: vmovdqu (%rdi), %xmm0
-; AVX1-NEXT: vpsadbw (%rsi), %xmm0, %xmm0
-; AVX1-NEXT: vmovdqu (%rdx), %xmm1
-; AVX1-NEXT: vpsadbw (%rcx), %xmm1, %xmm1
-; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
-; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
-; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vmovd %xmm0, %eax
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: sad_unroll_nonzero_initial:
-; AVX2: # %bb.0: # %bb
-; AVX2-NEXT: vmovdqu (%rdi), %xmm0
-; AVX2-NEXT: vpsadbw (%rsi), %xmm0, %xmm0
-; AVX2-NEXT: vmovdqu (%rdx), %xmm1
-; AVX2-NEXT: vpsadbw (%rcx), %xmm1, %xmm1
-; AVX2-NEXT: movl $1, %eax
-; AVX2-NEXT: vmovd %eax, %xmm2
-; AVX2-NEXT: vpaddd %xmm2, %xmm1, %xmm1
-; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
-; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
-; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX2-NEXT: vmovd %xmm0, %eax
-; AVX2-NEXT: retq
-;
-; AVX512-LABEL: sad_unroll_nonzero_initial:
-; AVX512: # %bb.0: # %bb
-; AVX512-NEXT: vmovdqu (%rdi), %xmm0
-; AVX512-NEXT: vpsadbw (%rsi), %xmm0, %xmm0
-; AVX512-NEXT: vmovdqu (%rdx), %xmm1
-; AVX512-NEXT: vpsadbw (%rcx), %xmm1, %xmm1
-; AVX512-NEXT: movl $1, %eax
-; AVX512-NEXT: vmovd %eax, %xmm2
-; AVX512-NEXT: vpaddd %xmm2, %xmm1, %xmm1
-; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
-; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
-; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vmovd %xmm0, %eax
-; AVX512-NEXT: retq
+; AVX-LABEL: sad_unroll_nonzero_initial:
+; AVX: # %bb.0: # %bb
+; AVX-NEXT: vmovdqu (%rdi), %xmm0
+; AVX-NEXT: vpsadbw (%rsi), %xmm0, %xmm0
+; AVX-NEXT: vmovdqu (%rdx), %xmm1
+; AVX-NEXT: vpsadbw (%rcx), %xmm1, %xmm1
+; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
+; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
+; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vmovd %xmm0, %eax
+; AVX-NEXT: retq
bb:
%tmp = load <16 x i8>, <16 x i8>* %arg, align 1
%tmp4 = load <16 x i8>, <16 x i8>* %arg1, align 1
diff --git a/llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll b/llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
index 1eee782f90ca..6c72adbc6317 100644
--- a/llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
+++ b/llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
@@ -325,7 +325,7 @@ define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuldq {{.*}}(%rip), %xmm1
-; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = <2454267027,u,0,u>
+; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2454267027,0,0,0]
; CHECK-SSE41-NEXT: pmuldq %xmm0, %xmm2
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
@@ -452,7 +452,7 @@ define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuldq {{.*}}(%rip), %xmm1
-; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = <2454267027,u,0,u>
+; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2454267027,0,0,0]
; CHECK-SSE41-NEXT: pmuldq %xmm0, %xmm2
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
@@ -1314,7 +1314,7 @@ define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {
; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuldq {{.*}}(%rip), %xmm1
-; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = <2454267027,u,0,u>
+; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2454267027,0,0,0]
; CHECK-SSE41-NEXT: pmuldq %xmm0, %xmm2
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
diff --git a/llvm/test/CodeGen/X86/vec_set-A.ll b/llvm/test/CodeGen/X86/vec_set-A.ll
index e246ef047231..c8ff250b5bfb 100644
--- a/llvm/test/CodeGen/X86/vec_set-A.ll
+++ b/llvm/test/CodeGen/X86/vec_set-A.ll
@@ -10,7 +10,7 @@ define <2 x i64> @test1() nounwind {
;
; X64-LABEL: test1:
; X64: # %bb.0:
-; X64-NEXT: movaps {{.*#+}} xmm0 = [1,0]
+; X64-NEXT: movaps {{.*#+}} xmm0 = [1,0,0,0]
; X64-NEXT: retq
ret <2 x i64> < i64 1, i64 0 >
}
diff --git a/llvm/test/CodeGen/X86/vec_shift2.ll b/llvm/test/CodeGen/X86/vec_shift2.ll
index 1f386bb5a1da..a38187f190f9 100644
--- a/llvm/test/CodeGen/X86/vec_shift2.ll
+++ b/llvm/test/CodeGen/X86/vec_shift2.ll
@@ -5,12 +5,12 @@
define <2 x i64> @t1(<2 x i64> %b1, <2 x i64> %c) nounwind {
; X32-LABEL: t1:
; X32: # %bb.0:
-; X32-NEXT: psrlw {{\.LCPI.*}}, %xmm0
+; X32-NEXT: psrlw $14, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: t1:
; X64: # %bb.0:
-; X64-NEXT: psrlw {{.*}}(%rip), %xmm0
+; X64-NEXT: psrlw $14, %xmm0
; X64-NEXT: retq
%tmp1 = bitcast <2 x i64> %b1 to <8 x i16>
%tmp2 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp1, <8 x i16> bitcast (<4 x i32> < i32 14, i32 undef, i32 undef, i32 undef > to <8 x i16>) ) nounwind readnone
diff --git a/llvm/test/CodeGen/X86/vector-lzcnt-128.ll b/llvm/test/CodeGen/X86/vector-lzcnt-128.ll
index ea77de539337..8c451b7215b0 100644
--- a/llvm/test/CodeGen/X86/vector-lzcnt-128.ll
+++ b/llvm/test/CodeGen/X86/vector-lzcnt-128.ll
@@ -1666,17 +1666,17 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
define <2 x i64> @foldv2i64() nounwind {
; SSE-LABEL: foldv2i64:
; SSE: # %bb.0:
-; SSE-NEXT: movaps {{.*#+}} xmm0 = [55,0]
+; SSE-NEXT: movaps {{.*#+}} xmm0 = [55,0,0,0]
; SSE-NEXT: retq
;
; NOBW-LABEL: foldv2i64:
; NOBW: # %bb.0:
-; NOBW-NEXT: vmovaps {{.*#+}} xmm0 = [55,0]
+; NOBW-NEXT: vmovaps {{.*#+}} xmm0 = [55,0,0,0]
; NOBW-NEXT: retq
;
; AVX512VLBWDQ-LABEL: foldv2i64:
; AVX512VLBWDQ: # %bb.0:
-; AVX512VLBWDQ-NEXT: vmovaps {{.*#+}} xmm0 = [55,0]
+; AVX512VLBWDQ-NEXT: vmovaps {{.*#+}} xmm0 = [55,0,0,0]
; AVX512VLBWDQ-NEXT: retq
;
; X32-SSE-LABEL: foldv2i64:
@@ -1690,17 +1690,17 @@ define <2 x i64> @foldv2i64() nounwind {
define <2 x i64> @foldv2i64u() nounwind {
; SSE-LABEL: foldv2i64u:
; SSE: # %bb.0:
-; SSE-NEXT: movaps {{.*#+}} xmm0 = [55,0]
+; SSE-NEXT: movaps {{.*#+}} xmm0 = [55,0,0,0]
; SSE-NEXT: retq
;
; NOBW-LABEL: foldv2i64u:
; NOBW: # %bb.0:
-; NOBW-NEXT: vmovaps {{.*#+}} xmm0 = [55,0]
+; NOBW-NEXT: vmovaps {{.*#+}} xmm0 = [55,0,0,0]
; NOBW-NEXT: retq
;
; AVX512VLBWDQ-LABEL: foldv2i64u:
; AVX512VLBWDQ: # %bb.0:
-; AVX512VLBWDQ-NEXT: vmovaps {{.*#+}} xmm0 = [55,0]
+; AVX512VLBWDQ-NEXT: vmovaps {{.*#+}} xmm0 = [55,0,0,0]
; AVX512VLBWDQ-NEXT: retq
;
; X32-SSE-LABEL: foldv2i64u:
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll b/llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
index 9d04c701ce6c..cd82cc89778b 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
@@ -713,8 +713,7 @@ define <16 x i16> @shuffle_v16i16_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_0
;
; AVX512VL-LABEL: shuffle_v16i16_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; AVX512VL: # %bb.0:
-; AVX512VL-NEXT: movl $15, %eax
-; AVX512VL-NEXT: vmovd %eax, %xmm1
+; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [15,0,0,0]
; AVX512VL-NEXT: vpermw %ymm0, %ymm1, %ymm0
; AVX512VL-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll b/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
index 0807aa6dab09..1cf048deca29 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
@@ -1600,24 +1600,21 @@ define <32 x i8> @shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
;
; AVX2-LABEL: shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; AVX2: # %bb.0:
+; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [15,0,0,0]
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,3,0,1]
-; AVX2-NEXT: movl $15, %eax
-; AVX2-NEXT: vmovd %eax, %xmm1
; AVX2-NEXT: vpshufb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512VLBW-LABEL: shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; AVX512VLBW: # %bb.0:
+; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm1 = [15,0,0,0]
; AVX512VLBW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,3,0,1]
-; AVX512VLBW-NEXT: movl $15, %eax
-; AVX512VLBW-NEXT: vmovd %eax, %xmm1
; AVX512VLBW-NEXT: vpshufb %ymm1, %ymm0, %ymm0
; AVX512VLBW-NEXT: retq
;
; AVX512VLVBMI-LABEL: shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; AVX512VLVBMI: # %bb.0:
-; AVX512VLVBMI-NEXT: movl $31, %eax
-; AVX512VLVBMI-NEXT: vmovd %eax, %xmm1
+; AVX512VLVBMI-NEXT: vmovdqa {{.*#+}} xmm1 = [31,0,0,0]
; AVX512VLVBMI-NEXT: vpermb %ymm0, %ymm1, %ymm0
; AVX512VLVBMI-NEXT: retq
;
@@ -1632,9 +1629,8 @@ define <32 x i8> @shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
;
; XOPAVX2-LABEL: shuffle_v32i8_31_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00:
; XOPAVX2: # %bb.0:
+; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [15,0,0,0]
; XOPAVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,3,0,1]
-; XOPAVX2-NEXT: movl $15, %eax
-; XOPAVX2-NEXT: vmovd %eax, %xmm1
; XOPAVX2-NEXT: vpshufb %ymm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
%shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 31, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
@@ -2791,7 +2787,7 @@ define <32 x i8> @shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
; AVX1-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_31_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16:
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [15,0,0,0]
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
@@ -2805,7 +2801,7 @@ define <32 x i8> @shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
; XOPAVX1-LABEL: shuffle_v32i8_15_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_31_16_16_16_16_16_16_16_16_16_16_16_16_16_16_16:
; XOPAVX1: # %bb.0:
; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
-; XOPAVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; XOPAVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [15,0,0,0]
; XOPAVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; XOPAVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; XOPAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll b/llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
index db36bdb5d940..4e62ffae6738 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
@@ -187,9 +187,8 @@ define <8 x float> @shuffle_v8f32_70000000(<8 x float> %a, <8 x float> %b) {
;
; AVX2OR512VL-LABEL: shuffle_v8f32_70000000:
; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: movl $7, %eax
-; AVX2OR512VL-NEXT: vmovd %eax, %xmm1
-; AVX2OR512VL-NEXT: vpermd %ymm0, %ymm1, %ymm0
+; AVX2OR512VL-NEXT: vmovaps {{.*#+}} xmm1 = [7,0,0,0]
+; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX2OR512VL-NEXT: retq
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x float> %shuffle
@@ -1510,9 +1509,8 @@ define <8 x i32> @shuffle_v8i32_70000000(<8 x i32> %a, <8 x i32> %b) {
;
; AVX2OR512VL-LABEL: shuffle_v8i32_70000000:
; AVX2OR512VL: # %bb.0:
-; AVX2OR512VL-NEXT: movl $7, %eax
-; AVX2OR512VL-NEXT: vmovd %eax, %xmm1
-; AVX2OR512VL-NEXT: vpermd %ymm0, %ymm1, %ymm0
+; AVX2OR512VL-NEXT: vmovaps {{.*#+}} xmm1 = [7,0,0,0]
+; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX2OR512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x i32> %shuffle
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll b/llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
index f798b55d7fd9..59c476901782 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
@@ -201,16 +201,14 @@ define <32 x i16> @shuffle_v32i16_03_00_01_02_07_04_05_06_11_08_09_10_15_12_13_1
define <32 x i16> @shuffle_v32i16_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz(<32 x i16> %a) {
; KNL-LABEL: shuffle_v32i16_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:
; KNL: ## %bb.0:
-; KNL-NEXT: movl $65535, %eax ## imm = 0xFFFF
-; KNL-NEXT: vmovd %eax, %xmm1
-; KNL-NEXT: vpand %ymm1, %ymm0, %ymm0
+; KNL-NEXT: vmovaps {{.*#+}} xmm1 = [65535,0,0,0]
+; KNL-NEXT: vandps %ymm1, %ymm0, %ymm0
; KNL-NEXT: retq
;
; SKX-LABEL: shuffle_v32i16_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:
; SKX: ## %bb.0:
-; SKX-NEXT: movl $65535, %eax ## imm = 0xFFFF
-; SKX-NEXT: vmovd %eax, %xmm1
-; SKX-NEXT: vpandq %zmm1, %zmm0, %zmm0
+; SKX-NEXT: vmovaps {{.*#+}} xmm1 = [65535,0,0,0]
+; SKX-NEXT: vandps %zmm1, %zmm0, %zmm0
; SKX-NEXT: retq
%shuffle = shufflevector <32 x i16> %a, <32 x i16> zeroinitializer, <32 x i32> <i32 0, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
ret <32 x i16> %shuffle
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll b/llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
index 191b29a19ce3..2cf8ab11ce27 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
@@ -109,9 +109,8 @@ define <64 x i8> @shuffle_v64i8_79_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_
define <64 x i8> @shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz(<64 x i8> %a) {
; AVX512F-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:
; AVX512F: # %bb.0:
-; AVX512F-NEXT: movl $255, %eax
-; AVX512F-NEXT: vmovd %eax, %xmm1
-; AVX512F-NEXT: vpand %ymm1, %ymm0, %ymm0
+; AVX512F-NEXT: vmovaps {{.*#+}} xmm1 = [255,0,0,0]
+; AVX512F-NEXT: vandps %ymm1, %ymm0, %ymm0
; AVX512F-NEXT: retq
;
; AVX512BW-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:
@@ -121,9 +120,8 @@ define <64 x i8> @shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz(<64 x i8> %a) {
;
; AVX512DQ-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:
; AVX512DQ: # %bb.0:
-; AVX512DQ-NEXT: movl $255, %eax
-; AVX512DQ-NEXT: vmovd %eax, %xmm1
-; AVX512DQ-NEXT: vpand %ymm1, %ymm0, %ymm0
+; AVX512DQ-NEXT: vmovaps {{.*#+}} xmm1 = [255,0,0,0]
+; AVX512DQ-NEXT: vandps %ymm1, %ymm0, %ymm0
; AVX512DQ-NEXT: retq
;
; AVX512VBMI-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll b/llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
index 739ea6bae535..f582a31a607d 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
@@ -142,9 +142,8 @@ define <8 x double> @shuffle_v8f64_06000000(<8 x double> %a, <8 x double> %b) {
define <8 x double> @shuffle_v8f64_70000000(<8 x double> %a, <8 x double> %b) {
; ALL-LABEL: shuffle_v8f64_70000000:
; ALL: # %bb.0:
-; ALL-NEXT: movl $7, %eax
-; ALL-NEXT: vmovd %eax, %xmm1
-; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0
+; ALL-NEXT: vmovaps {{.*#+}} xmm1 = [7,0,0,0]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x double> %shuffle
@@ -961,9 +960,8 @@ define <8 x i64> @shuffle_v8i64_06000000(<8 x i64> %a, <8 x i64> %b) {
define <8 x i64> @shuffle_v8i64_70000000(<8 x i64> %a, <8 x i64> %b) {
; ALL-LABEL: shuffle_v8i64_70000000:
; ALL: # %bb.0:
-; ALL-NEXT: movl $7, %eax
-; ALL-NEXT: vmovd %eax, %xmm1
-; ALL-NEXT: vpermq %zmm0, %zmm1, %zmm0
+; ALL-NEXT: vmovaps {{.*#+}} xmm1 = [7,0,0,0]
+; ALL-NEXT: vpermpd %zmm0, %zmm1, %zmm0
; ALL-NEXT: ret{{[l|q]}}
%shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x i64> %shuffle
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
index 257bd03dee8e..dd1f766dcf66 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
@@ -899,12 +899,10 @@ define <8 x double> @combine_vpermi2var_vpermt2var_8f64_as_vperm2(<8 x double> %
define <8 x double> @combine_vpermi2var_8f64_as_permpd(<8 x double> %x0, <8 x double> %x1, i64 %a2) {
; X86-LABEL: combine_vpermi2var_8f64_as_permpd:
; X86: # %bb.0:
-; X86-NEXT: movl $2, %eax
-; X86-NEXT: vmovd %eax, %xmm2
-; X86-NEXT: vmovq {{.*#+}} xmm3 = mem[0],zero
-; X86-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
-; X86-NEXT: vinserti128 $1, {{\.LCPI.*}}, %ymm2, %ymm2
-; X86-NEXT: vinserti64x4 $1, {{\.LCPI.*}}, %zmm2, %zmm2
+; X86-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
+; X86-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm2[0],mem[0]
+; X86-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm2, %ymm2
+; X86-NEXT: vinsertf64x4 $1, {{\.LCPI.*}}, %zmm2, %zmm2
; X86-NEXT: vpermi2pd %zmm1, %zmm0, %zmm2
; X86-NEXT: vpermpd {{.*#+}} zmm0 = zmm2[2,3,1,1,6,7,5,5]
; X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
index 9c507ad5443e..4a10a20bc5ff 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
@@ -131,27 +131,14 @@ define <4 x double> @combine_vpermil2pd256_as_shufpd(<4 x double> %a0, <4 x doub
}
define <4 x double> @demandedelts_vpermil2pd256_as_shufpd(<4 x double> %a0, <4 x double> %a1, i64 %a2) {
-; X86-AVX-LABEL: demandedelts_vpermil2pd256_as_shufpd:
-; X86-AVX: # %bb.0:
-; X86-AVX-NEXT: movl $4, %eax
-; X86-AVX-NEXT: vmovd %eax, %xmm2
-; X86-AVX-NEXT: vmovq {{.*#+}} xmm3 = mem[0],zero
-; X86-AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
-; X86-AVX-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm2, %ymm2
-; X86-AVX-NEXT: vpermil2pd $0, %ymm2, %ymm1, %ymm0, %ymm0
-; X86-AVX-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,1,2,3]
-; X86-AVX-NEXT: retl
-;
-; X86-AVX2-LABEL: demandedelts_vpermil2pd256_as_shufpd:
-; X86-AVX2: # %bb.0:
-; X86-AVX2-NEXT: movl $4, %eax
-; X86-AVX2-NEXT: vmovd %eax, %xmm2
-; X86-AVX2-NEXT: vmovq {{.*#+}} xmm3 = mem[0],zero
-; X86-AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
-; X86-AVX2-NEXT: vinserti128 $1, {{\.LCPI.*}}, %ymm2, %ymm2
-; X86-AVX2-NEXT: vpermil2pd $0, %ymm2, %ymm1, %ymm0, %ymm0
-; X86-AVX2-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,1,2,3]
-; X86-AVX2-NEXT: retl
+; X86-LABEL: demandedelts_vpermil2pd256_as_shufpd:
+; X86: # %bb.0:
+; X86-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
+; X86-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm2[0],mem[0]
+; X86-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm2, %ymm2
+; X86-NEXT: vpermil2pd $0, %ymm2, %ymm1, %ymm0, %ymm0
+; X86-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,1,2,3]
+; X86-NEXT: retl
;
; X64-LABEL: demandedelts_vpermil2pd256_as_shufpd:
; X64: # %bb.0:
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-v1.ll b/llvm/test/CodeGen/X86/vector-shuffle-v1.ll
index c51197109620..8ab57bf78a6f 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-v1.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-v1.ll
@@ -46,7 +46,7 @@ define <2 x i1> @shuf2i1_1_2(<2 x i1> %a) {
; AVX512F-NEXT: vpsllq $63, %xmm0, %xmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
-; AVX512F-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
+; AVX512F-NEXT: vmovdqa {{.*#+}} xmm1 = [18446744073709551615,0]
; AVX512F-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7]
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
@@ -60,8 +60,7 @@ define <2 x i1> @shuf2i1_1_2(<2 x i1> %a) {
; AVX512VL-NEXT: vptestmq %xmm0, %xmm0, %k1
; AVX512VL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VL-NEXT: vmovdqa64 %xmm0, %xmm1 {%k1} {z}
-; AVX512VL-NEXT: movq $-1, %rax
-; AVX512VL-NEXT: vmovq %rax, %xmm2
+; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm2 = [18446744073709551615,0]
; AVX512VL-NEXT: vpalignr {{.*#+}} xmm1 = xmm1[8,9,10,11,12,13,14,15],xmm2[0,1,2,3,4,5,6,7]
; AVX512VL-NEXT: vptestmq %xmm1, %xmm1, %k1
; AVX512VL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
@@ -71,10 +70,9 @@ define <2 x i1> @shuf2i1_1_2(<2 x i1> %a) {
; VL_BW_DQ: # %bb.0:
; VL_BW_DQ-NEXT: vpsllq $63, %xmm0, %xmm0
; VL_BW_DQ-NEXT: vpmovq2m %xmm0, %k0
-; VL_BW_DQ-NEXT: movq $-1, %rax
-; VL_BW_DQ-NEXT: vmovq %rax, %xmm0
-; VL_BW_DQ-NEXT: vpmovm2q %k0, %xmm1
-; VL_BW_DQ-NEXT: vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
+; VL_BW_DQ-NEXT: vpmovm2q %k0, %xmm0
+; VL_BW_DQ-NEXT: vmovdqa {{.*#+}} xmm1 = [18446744073709551615,0]
+; VL_BW_DQ-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7]
; VL_BW_DQ-NEXT: vpmovq2m %xmm0, %k0
; VL_BW_DQ-NEXT: vpmovm2q %k0, %xmm0
; VL_BW_DQ-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-tzcnt-128.ll b/llvm/test/CodeGen/X86/vector-tzcnt-128.ll
index 91301f319b02..5a0507a71799 100644
--- a/llvm/test/CodeGen/X86/vector-tzcnt-128.ll
+++ b/llvm/test/CodeGen/X86/vector-tzcnt-128.ll
@@ -1576,32 +1576,32 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
define <2 x i64> @foldv2i64() nounwind {
; SSE-LABEL: foldv2i64:
; SSE: # %bb.0:
-; SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0]
+; SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,0,0]
; SSE-NEXT: retq
;
; AVX-LABEL: foldv2i64:
; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0]
; AVX-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: foldv2i64:
; AVX512VPOPCNTDQ: # %bb.0:
-; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
+; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0]
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: foldv2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
-; AVX512VPOPCNTDQVL-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
+; AVX512VPOPCNTDQVL-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0]
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: foldv2i64:
; BITALG_NOVLX: # %bb.0:
-; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
+; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0]
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: foldv2i64:
; BITALG: # %bb.0:
-; BITALG-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
+; BITALG-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0]
; BITALG-NEXT: retq
;
; X32-SSE-LABEL: foldv2i64:
@@ -1615,32 +1615,32 @@ define <2 x i64> @foldv2i64() nounwind {
define <2 x i64> @foldv2i64u() nounwind {
; SSE-LABEL: foldv2i64u:
; SSE: # %bb.0:
-; SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0]
+; SSE-NEXT: movaps {{.*#+}} xmm0 = [8,0,0,0]
; SSE-NEXT: retq
;
; AVX-LABEL: foldv2i64u:
; AVX: # %bb.0:
-; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
+; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0]
; AVX-NEXT: retq
;
; AVX512VPOPCNTDQ-LABEL: foldv2i64u:
; AVX512VPOPCNTDQ: # %bb.0:
-; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
+; AVX512VPOPCNTDQ-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0]
; AVX512VPOPCNTDQ-NEXT: retq
;
; AVX512VPOPCNTDQVL-LABEL: foldv2i64u:
; AVX512VPOPCNTDQVL: # %bb.0:
-; AVX512VPOPCNTDQVL-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
+; AVX512VPOPCNTDQVL-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0]
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: foldv2i64u:
; BITALG_NOVLX: # %bb.0:
-; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
+; BITALG_NOVLX-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0]
; BITALG_NOVLX-NEXT: retq
;
; BITALG-LABEL: foldv2i64u:
; BITALG: # %bb.0:
-; BITALG-NEXT: vmovaps {{.*#+}} xmm0 = [8,0]
+; BITALG-NEXT: vmovaps {{.*#+}} xmm0 = [8,0,0,0]
; BITALG-NEXT: retq
;
; X32-SSE-LABEL: foldv2i64u:
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