[llvm] 76e3dd0 - AMDGPU: Implement isConstantPhysReg

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-05-23T13:24:42-04:00
New Revision: 76e3dd0a490d7da25ccf35c29b3b7ec34908f7d6

URL: https://github.com/llvm/llvm-project/commit/76e3dd0a490d7da25ccf35c29b3b7ec34908f7d6
DIFF: https://github.com/llvm/llvm-project/commit/76e3dd0a490d7da25ccf35c29b3b7ec34908f7d6.diff

LOG: AMDGPU: Implement isConstantPhysReg

I don't think any of these registers are used in contexts where this
would do anything yet.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    llvm/lib/Target/AMDGPU/SIRegisterInfo.h

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 9001967863da..7657a2d0ea2c 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1849,3 +1849,16 @@ MCPhysReg SIRegisterInfo::get32BitRegister(MCPhysReg Reg) const {
 
   return AMDGPU::NoRegister;
 }
+
+bool SIRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
+  switch (PhysReg) {
+  case AMDGPU::SGPR_NULL:
+  case AMDGPU::SRC_SHARED_BASE:
+  case AMDGPU::SRC_PRIVATE_BASE:
+  case AMDGPU::SRC_SHARED_LIMIT:
+  case AMDGPU::SRC_PRIVATE_LIMIT:
+    return true;
+  default:
+    return false;
+  }
+}

diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 55ea00a246a1..0b2920b3777e 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -210,6 +210,8 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
     return isVGPR(MRI, Reg) || isAGPR(MRI, Reg);
   }
 
+  bool isConstantPhysReg(MCRegister PhysReg) const override;
+
   bool isDivergentRegClass(const TargetRegisterClass *RC) const override {
     return !isSGPRClass(RC);
   }