[PATCH] D80466: [X86] Improve i8 + 'slow' i16 funnel shift codegen

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, spatel, lebedev.ri.
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This is a preliminary patch before I deal with the xor+and issue raised in D77301 <https://reviews.llvm.org/D77301>.

We get much better code for i8/i16 funnel shifts by concatenating the operands together and performing the shift as a double width type, it avoids repeated use of the shift amount and partial registers.

  fshl(x,y,z) -> (((zext(x) << bw) | zext(y)) << (z & (bw-1))) >> bw.
  fshr(x,y,z) -> (((zext(x) << bw) | zext(y)) >> (z & (bw-1))) >> bw.

Alive2: http://volta.cs.utah.edu:8080/z/CZx7Cn

This doesn't do as well for i32 cases on x86_64 (the xor+and followup patch is much better) so I haven't bothered with that.

Cases with constant amounts are more dubious as well so I haven't currently bothered with those - its these kind of 'edge' cases that put me off trying to put this in TargetLowering::expandFunnelShift.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80466

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/fshl.ll
  llvm/test/CodeGen/X86/fshr.ll
  llvm/test/CodeGen/X86/rotate-extract.ll

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