[PATCH] D72175: AMDGPU: Define mode register

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D72175#2050379 <https://reviews.llvm.org/D72175#2050379>, @arsenm wrote:

> Unlike HSAIL, in LLVM the FP mode is going to be a middle end, IR problem. The backend won't be responsible for inserting or maintaining mode switches. All of that should be done in the IR on the constrained FP intrinsics. Separately tracking the bits on the machine level is going to increase the cost and complexity too much (just the one I think is too much, but manageable)


Well, actually it was in the SC, so backend. The point to split it is to be able to reschedule without false dependencies and to minimize required switches. At the very least we need to minimize switches.


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