[PATCH] D80091: AMDGPU/GlobalISel: Fix masked control flow with fallthrough blocks

[Matt Arsenault via Phabricator via llvm-commits]

arsenm marked 2 inline comments as done.
arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll:40
 ; CHECK-NEXT:    s_and_saveexec_b64 s[4:5], vcc
-; CHECK-NEXT:    s_cbranch_execnz BB1_2
+; CHECK-NEXT:    s_cbranch_execz BB1_2
 ; CHECK-NEXT:  ; %bb.1: ; %if.true
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sameerds wrote:
> For this and all other similar updates, does this mean that the existing testcases were actually wrong?
Yes


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir:232
+  ; WAVE64:   S_NOP 0
+  ; WAVE64:   SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+  ; WAVE64:   G_BR %bb.1
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sameerds wrote:
> "backward" is a bit of an understatement when describing this very interesting artifact. I don't know the SI intrinsics very well, but the name suggests it should be a backedge. But this use suggests that the meaning is more general than that: the presence of SI_LOOP instead of a simple conditional branch indicates that the edge is either a backedge or a loop exit.
Yes, I've been confused by this every time I've ever looked at this. If you look at how SI_LOOP is lowered, it's the s_cbranch_execnz which should be the backedge, but the loop intrinsic on return true exits the loop


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80091/new/

https://reviews.llvm.org/D80091