[llvm] 9301e3a - [Target] Fix typos. NFC
Marek Kurdej via llvm-commits
llvm-commits at lists.llvm.org
Fri May 22 05:42:56 PDT 2020
Author: Marek Kurdej
Date: 2020-05-22T14:40:43+02:00
New Revision: 9301e3aaca5986fd9517c6e35704a1619dc35694
URL: https://github.com/llvm/llvm-project/commit/9301e3aaca5986fd9517c6e35704a1619dc35694
DIFF: https://github.com/llvm/llvm-project/commit/9301e3aaca5986fd9517c6e35704a1619dc35694.diff
LOG: [Target] Fix typos. NFC
Added:
Modified:
llvm/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index d1f3573cb537..d6c1efa6327c 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1106,7 +1106,7 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
// 1) for Thumb1 code we sometimes materialize the constant via constpool
// load.
// 2) for Thumb2 execute only code we materialize the constant via
- // immediate constants in 2 seperate instructions (MOVW/MOVT).
+ // immediate constants in 2 separate instructions (MOVW/MOVT).
SrcReg = ~0U;
DstReg = MI->getOperand(0).getReg();
break;
diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index 02618b3529c9..fa1ba4f2e469 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -1064,7 +1064,7 @@ bool HexagonPacketizerList::ignorePseudoInstruction(const MachineInstr &MI,
}
bool HexagonPacketizerList::isSoloInstruction(const MachineInstr &MI) {
- // Ensure any bundles created by gather packetize remain seperate.
+ // Ensure any bundles created by gather packetize remain separate.
if (MI.isBundle())
return true;
diff --git a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
index a0cef92feff6..4fbad613288a 100644
--- a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
+++ b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
@@ -442,7 +442,7 @@ class WebAssemblyAsmParser final : public MCTargetAsmParser {
Name = StringRef(NameLoc.getPointer(), Name.size());
// WebAssembly has instructions with / in them, which AsmLexer parses
- // as seperate tokens, so if we find such tokens immediately adjacent (no
+ // as separate tokens, so if we find such tokens immediately adjacent (no
// whitespace), expand the name to include them:
for (;;) {
auto &Sep = Lexer.getTok();
@@ -700,7 +700,7 @@ class WebAssemblyAsmParser final : public MCTargetAsmParser {
// WebAssemblyAsmPrinter::EmitFunctionBodyStart.
// TODO: would be good to factor this into a common function, but the
// assembler and backend really don't share any common code, and this code
- // parses the locals seperately.
+ // parses the locals separately.
auto SymName = expectIdent();
if (SymName.empty())
return true;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
index 07f183c0e1a1..eedc2c0b8a98 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
@@ -318,7 +318,7 @@ static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI) {
// Remove all uses of stackified registers to bring the instruction format
// into its final stack form used thruout MC, and transition opcodes to
// their _S variant.
- // We do this seperate from the above code that still may need these
+ // We do this separate from the above code that still may need these
// registers for e.g. call_indirect signatures.
// See comments in lib/Target/WebAssembly/WebAssemblyInstrFormats.td for
// details.
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