[PATCH] D80364: [amdgpu] Teach load widening to handle non-DWORD aligned loads.
Michael Liao via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu May 21 11:54:07 PDT 2020
hliao marked an inline comment as done.
hliao added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:7472-7475
+ std::tie(AD, RC) =
+ MFI->getPreloadedValue(AMDGPUFunctionArgInfo::DISPATCH_PTR);
+ if (AD && AD->isRegister() && AD->getRegister() == Reg)
+ return true;
----------------
hliao wrote:
> arsenm wrote:
> > This will be true for all of the preloaded SGPRs. However I think looking for the argument copies here is the wrong approach. The original intrinsic calls should have been annotated with the align return value attribute. Currently this is a burden on the frontend/library call emitting the intrinsic. We could either annotate the intrinsic calls in one of the later passes (maybe AMDGPUCodeGenPrepare), or add a minimum alignment to the intrinsic definition which will always be applied, similar to how intrinsic declarations already get their other attributes
> do we have that attribute available? could you elaborate in detail?
OK, I found that.
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https://reviews.llvm.org/D80364/new/
https://reviews.llvm.org/D80364
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