[PATCH] D80384: [SVE] Add flag to specify SVE register size, using this to calculate legal vector types.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm created this revision.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.

Adds aarch64-sve-vector-bits-{min,max} to allow the size of SVE
data registers (in bits) to be specified. This allows the code
generator to make assumptions it normally couldn't. As a starting
point this information is used to mark fixed length vector types
that can fit within the specified size as legal.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80384

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
  llvm/test/Analysis/CostModel/AArch64/sve-fixed-length.ll

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